Method to fabricate split-gate with self-aligned source and self-aligned floating gate to control gate

• US 6,228,695 B1
• Filed: 05/27/1999
• Issued: 05/08/2001
• Est. Priority Date: 05/27/1999
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hsieh, Chia-Ta, Sung, Hung-Cheng, Kuo, Di-Son, Yeh, Jack, Lin, Yai-Fen
• Primary Examiner(s): QUACH, TUAN N
• Application Number:
  US09/320,759
• Time in Patent Office: 712 Days
• Field of Search: 438/201, 438/211, 438/257
• US Class Current: 438/201
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A split-gate flash memory cell having self-aligned source and floating gate self-aligned to control gate is disclosed as well as a method of forming the same. This is accomplished by depositing over a gate oxide layer on a silicon substrate a poly-1 layer to form a vertical control gate followed by depositing a poly-2 layer to form a spacer floating gate adjacent to the control gate with an intervening intergate oxide layer. The source is self-aligned and the floating gate is also formed to be self-aligned to the control gate, thus making it possible to reduce the cell size. The resulting self-aligned source alleviates punch-through from source to control gate while the self-aligned floating gate with respect to the control gate provides improved programmability. The method also replaces the conventional poly oxidation process thereby yielding improved sharp peak of floating gate for improved erasing and writing of the split-gate flash memory cell.

Claims

1. A method of forming split-gate flash memory cell having a self-aligned source as well as a floating gate self-aligned to control gate comprising the steps of:

providing a silicon substrate having a plurality of active and field oxide isolation regions defined by shallow trench isolation (STI) regions;

forming a first gate oxide layer over said substrate;

forming a first polysilicon (poly-1) layer over said first gate oxide layer;

forming a silicide layer over said poly-1 layer;

forming a tetraethyl orthosilicate (TEOS) layer over said silicide layer;

forming a first photoresist layer over said TEOS layer;

patterning said first photoresist layer to define a control gate area;

etching said TEOS layer and said silicide layer through said patterning in said first photoresist layer and forming opening in said TEOS layer exposing portion of said poly-1 layer;

etching said exposed portion of said poly-1 layer and forming a control gate;

removing said first photoresist layer;

forming a second gate oxide layer over said substrate;

forming a partial-depth second polysilicon (poly-2) layer over said second gate oxide layer;

etching said partial-depth poly-2 layer to form a drain spacer and a source spacer and a sharp peak therein;

forming a second photoresist layer over said substrate to define a self-aligned source (SAS) region;

etching partially said field oxide isolation layer through said second photoresist layer in said SAS region;

removing said second photoresist layer;

forming a third photoresist layer over said substrate with openings exposing said poly-2 drain spacer and said poly-2 covering said STI regions;

etching through said openings in said third photoresist layer to remove said poly-2 drain spacer and said poly-2 covering said STI regions to form a floating gate cell;

forming a fourth photoresist layer over said substrate to redefine a self-aligned source (SAS) region;

etching completely said field oxide isolation layer through said fourth photoresist layer until said silicon substrate is reached in said SAS region;

ion implanting said SAS region;

removing said fourth photoresist layer;

annealing said silicide layer;

forming a drain in said substrate;

forming an interlevel dielectric layer (ILD) over said substrate; and

forming a metal contact in said ILD layer to complete the forming of said split-gate flash memory cell.

2. The method of claim 1, wherein said forming said first gate oxide layer is accomplished by thermal growth at a temperature between about 850 to 950°

C.

3. The method of claim 2, wherein said gate oxide layer has a thickness between about 190 to 210 angstroms (Å

).

4. The method of claim 1, wherein said forming a poly-1 layer is accomplished with silicon source SiH₄ using LPCVD at a temperature between about 550 to 620°

C.

5. The method of claim 1, wherein said poly-1 layer has a thickness between about 900 to 1100 angstroms (Å

).

6. The method of claim 1, wherein said forming silicide is accomplished by co-sputtering tungsten and silicon.

7. The method of claim 6, wherein the thickness of said silicide layer is between about 800 to 1500 Å

.

8. The method of claim 1, wherein said forming said TEOS layer is accomplished by decomposing tetraethyl orthosilicate at a temperature between about 600-650°

C.

9. The method of claim 1, wherein said TEOS layer has a thickness between about 1900 to 2100 Å

.

10. The method of claim 1, wherein said etching said TEOS layer is accomplished with etch recipe comprising O₂ gas.

11. The method of claim 1, wherein said etching said exposed portion of said poly-1 layer is accomplished with a recipe comprising gases containing HBr, Cl₂, He and O₂.

12. The method of claim 1, wherein said forming said second gate oxide layer is accomplished by thermal growth at a temperature between about 850 to 950°

C.

13. The method of claim 1, wherein said second oxide layer has a thickness between about 70 to 90 Å

.

14. The method of claim 1, wherein said forming said partial-depth poly-2 layer is accomplished with silicon source SiH₄ using LPCVD at a temperature between about 550 to 620°

C.

15. The method of claim 1, wherein said partial-depth poly-2 layer has a thickness between about 1900 to 2100 Å

.

16. The method of claim 1, wherein said etching said partial-depth poly-2 layer to form drain spacer and source spacer is accomplished with gases containing O₂, HBr, Cl₂ and He.

17. The method of claim 1, wherein said etching partially said second gate oxide layer is accomplished with gases containing CF₄, CHF₃ and O₂.

18. The method of claim 1, wherein said etching partially said isolation oxide layer is performed until said isolation oxide layer has a thickness between about 300 to 600 Å

.

19. The method of claim 1, wherein said etching through said openings in said third photoresist layer to remove said poly-2 drain spacer and said poly-2 covering said STI regions to form floating gate cell is accomplished with gases containing O₂, HBr, Cl₂ and He.

20. The method of claim 1, wherein said etching completely said isolation oxide layer through fourth photoresist layer in said SAS region is accomplished with gases containing CF₄, CHF₃ and O₂.

21. The method of claim 1, wherein said ion implanting said SAS region is accomplished by implanting phosphorous ions with a dosage between about 1×

10¹⁵ to 9×

10¹⁵ atoms/cm² and at an energy between about 10 to 60 KeV.

22. The method of claim 1, wherein said annealing said silicide layer is accomplished at a temperature between about 800 to 900°

C.

23. The method of claim 1, wherein said forming said drain is accomplished by implanting arsenic ions at a dosage level between about 1×

10¹⁵ to 9×

10¹⁵atoms/cm² with energy level between about 10 to 60 KeV.

24. The method of claim 1, wherein said forming said interlevel ILD layer is accomplished by depositing an oxide layer to a thickness between about 10,000 to 15,000 Å

.

25. The method of claim 1, wherein said forming said metal contact in said ILD layer is accomplished by patterning said ILD layer with contact hole pattern and then filling with metal.