Fabrication of metal oxide structures with different thicknesses on a semiconductor substrate

• US 6,228,721 B1
• Filed: 06/26/2000
• Issued: 05/08/2001
• Est. Priority Date: 06/26/2000
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Yu, Bin
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US09/602,666
• Time in Patent Office: 316 Days
• Field of Search: 438/275, 438/276, 438/277, 438/278, 438/289, 438/296, 438/981
• US Class Current: 438/275
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: Y10S 438/981 Utilizing varying dielectric thickness

Abstract

For fabricating a metal oxide structure on a semiconductor substrate, an active device area surrounded by at least one STI (shallow trench isolation) structure is formed in the semiconductor substrate. A layer of metal is deposited on the semiconductor substrate, and the layer of metal contacts the active device area of the semiconductor substrate. A layer of oxygen blocking material is deposited on the layer of metal. An opening is etched through the layer of oxygen blocking material to expose an area of the layer of metal on top of the active device area. A thermal oxidation process is performed to form a metal oxide structure from reaction of oxygen with the area of the layer of metal that is exposed. A thickness of the metal oxide structure is determined by a thickness of the layer of metal, and the layer of oxygen blocking material prevents contact of oxygen with the layer of metal such that the metal oxide structure is formed localized at the area where the layer of metal is exposed. In this manner, the metal oxide structure is formed by localized thermal oxidation of the layer of metal such that a deposition or sputtering process or an etching process is not necessary for formation of the metal oxide structure. In addition, the thickness of the metal oxide structure is determined by controlling the thickness of the layer of metal used for forming the metal oxide structure. Furthermore, these steps may be repeated for another layer of metal having a different thickness for forming a plurality of metal oxide structures having different thicknesses to provide gate dielectrics of MOSFETs (metal oxide semiconductor field effect transistors) having different threshold voltages on the same semiconductor substrate.

Claims

1. A method for fabricating at least one metal oxide structure on a semiconductor substrate, the method including the steps of:

A. forming a first active device area surrounded by at least one STI (shallow trench isolation) structure in said semiconductor substrate;

B. depositing a first layer of metal on said semiconductor substrate, wherein said first layer of metal contacts said first active device area of said semiconductor substrate;

C. depositing a first layer of oxygen blocking material on said first layer of metal;

D. etching a first opening through said first layer of oxygen blocking material to expose a first area of said first layer of metal on top of said first active device area; and

E. performing a first thermal oxidation process to form a first metal oxide structure from reaction of oxygen with said first area of said first layer of metal, wherein a thickness of said first metal oxide structure is determined by a thickness of said first layer of metal, and wherein said first layer of oxygen blocking material prevents contact of oxygen with said first layer of metal such that said first metal oxide structure is formed localized at said first area where said first layer of metal is exposed.

2. The method of claim 1, further including the steps of:

F. etching away said first layer of oxygen blocking material and said first layer of metal;

G. forming a second active device area surrounded by at least one STI (shallow trench isolation) structure in said semiconductor substrate;

H. forming a second layer of oxygen blocking material to cover said first active device area, wherein said second active device area is exposed;

I. depositing a second layer of metal across structures of said semiconductor substrate, wherein said second layer of metal contacts said second active device area of said semiconductor substrate;

J. depositing a third layer of oxygen blocking material on said second layer of metal;

K. etching a second opening through said third layer of oxygen blocking material to expose a second area of said second layer of metal on top of said second active device area; and

L. performing a second thermal oxidation process to form a second metal oxide structure from reaction of oxygen with said second area of said second layer of metal, wherein a thickness of said second metal oxide structure is determined by a thickness of said second layer of metal, and wherein said third layer of oxygen blocking material prevents contact of oxygen with said second layer of metal such that said second metal oxide structure is formed localized at said second area where said second layer of metal is exposed.

3. The method of claim 2, wherein the thickness of said first metal oxide structure is different from the thickness of said second metal oxide structure.

4. The method of claim 2, wherein said first metal oxide structure is comprised of one of aluminum oxide (Al₂O₃), titanium oxide (TiO₂), and tantalum oxide (Ta₂O₅).

5. The method of claim 2, wherein said second metal oxide structure is comprised of one of aluminum oxide (Al₂O₃), titanium oxide (TiO₂), and tantalum oxide (Ta₂O₅).

6. The method of claim 2, wherein said first, second, and third layers of oxygen blocking material are comprised of silicon nitride (SiN).

7. The method of claim 2, wherein the thickness of said first metal oxide structure and the thickness of said second metal oxide structure are in a range of from about 150 Å

(angstroms) to about 180 Å

(angstroms).

8. The method of claim 2, wherein said first thermal oxidation process and said second thermal oxidation process are performed with a temperature in a range of from about 250°

Celsius to about 300°

Celsius.

9. The method of claim 2, wherein the thickness of said first metal oxide structure is less than the thickness of said second metal oxide structure, and wherein said first metal oxide structure is a gate dielectric of a first MOSFET (metal oxide semiconductor field effect transistor) having a first threshold voltage, and wherein said second metal oxide structure is a gate dielectric of a second MOSFET (metal oxide semiconductor field effect transistor) having a second threshold voltage, and wherein said first threshold voltage is less than said second threshold voltage.

10. The method of claim 1, wherein said first metal oxide structure is comprised of one of aluminum oxide (Al₂O₃), titanium oxide (TiO₂), and tantalum oxide (Ta₂O₅).

11. The method of claim 1, wherein said first layer of oxygen blocking material is comprised of silicon nitride (SiN).

12. The method of claim 1, wherein the thickness of said first metal oxide structure is in a range of from about 150 Å

(angstroms) to about 180 Å

(angstroms).

13. The method of claim 2, wherein said first thermal oxidation process is performed with a temperature in a range of from about 250°

Celsius to about 300°

Celsius.

14. A method for fabricating a plurality of metal oxide structures having different thicknesses on a semiconductor substrate, the method including the steps of:

A. forming a first active device area surrounded by at least one STI (shallow trench isolation) structure in said semiconductor substrate;

B. forming a second active device area surrounded by at least one STI (shallow trench isolation) structure in said semiconductor substrate;

C. depositing a first layer of metal on said semiconductor substrate, wherein said first layer of metal contacts said first active device area of said semiconductor substrate;

D. depositing a first layer of oxygen blocking material on said first layer of metal;

E. etching a first opening through said first layer of oxygen blocking material to expose a first area of said first layer of metal on top of said first active device area;

F. performing a first thermal oxidation process to form a first metal oxide structure from reaction of oxygen with said first area of said first layer of metal, wherein a thickness of said first metal oxide structure is determined by a thickness of said first layer of metal, and wherein said first layer of oxygen blocking material prevents contact of oxygen with said first layer of metal such that said first metal oxide structure is formed localized at said first area where said first layer of metal is exposed;

G. etching away said first layer of oxygen blocking material and said first layer of metal;

H. forming a second layer of oxygen blocking material to cover said first active device area, wherein said second active device area is exposed;

I. depositing a second layer of metal across structures of said semiconductor substrate, wherein said second layer of metal contacts said second active device area of said semiconductor substrate;

J. depositing a third layer of oxygen blocking material on said second layer of metal;

K. etching a second opening through said third layer of oxygen blocking material to expose a second area of said second layer of metal on top of said second active device area; and

L. performing a second thermal oxidation process to form a second metal oxide structure from reaction of oxygen with said second area of said second layer of metal, wherein a thickness of said second metal oxide structure is determined by a thickness of said second layer of metal, and wherein said second layer of oxygen blocking material prevents contact of oxygen with said second layer of metal such that said second metal oxide structure is formed localized at said second area where said second layer of metal is exposed;

and wherein the thickness of said first metal oxide structure is different from the thickness of said second metal oxide structure;

and wherein said first metal oxide structure and said second metal oxide structure are comprised of one of aluminum oxide (Al₂O₃), titanium oxide (TiO₂), and tantalum oxide (Ta₂O₅);

and wherein said first, second, and third layers of oxygen blocking material are comprised of silicon nitride (SiN);

and wherein the thickness of said first metal oxide structure and the thickness of said second metal oxide structure are in a range of from about 150 Å

(angstroms) to about 180 Å

(angstroms);

and wherein said first thermal oxidation process and said second thermal oxidation process are performed with a temperature in a range of from about 250°

Celsius to about 300°

Celsius;

and wherein the thickness of said first metal oxide structure is less than the thickness of said second metal oxide structure, and wherein said first metal oxide structure is a gate dielectric of a first MOSFET (metal oxide semiconductor field effect transistor) having a first threshold voltage, and wherein said second metal oxide structure is a gate dielectric of a second MOSFET (metal oxide semiconductor field effect transistor) having a second threshold voltage, and wherein said first threshold voltage is less than said second threshold voltage.