Method to form shallow trench isolations with rounded corners and reduced trench oxide recess

• US 6,228,727 B1
• Filed: 09/27/1999
• Issued: 05/08/2001
• Est. Priority Date: 09/27/1999
• Status: Expired due to Term

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Inventors: Lim, Chong Wee, Lee, Kong-Hean, Low, Chun Hui, Lim, Eng Hua, Siah, Soh Yun
• Primary Examiner(s): Tsai, Jey
• Assistant Examiner(s): JONES, JOSETTA I
• Application Number:
  US09/405,061
• Time in Patent Office: 589 Days
• Field of Search: 438/296, 438/424, 438/445
• US Class Current: 438/296
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/02304 formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/31612 on a silicon body
• CPC Class Codes: H01L 21/32 using masks
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence

Abstract

A method of fabricating shallow trench isolations has been achieved. A semiconductor substrate is provided. A pad oxide layer is grown overlying the semiconductor substrate. A silicon nitride layer is deposited. The silicon nitride layer and the pad oxide layer are patterned to form a hard mask. The openings in the hard mask correspond to planned trenches in the semiconductor substrate. A silicon dioxide layer is deposited overlying the silicon nitride layer and the semiconductor substrate. The silicon dioxide layer is anisotropically etched to form sidewall spacers on the inside of the openings of the hard mask. The semiconductor substrate is etched to form the trenches. The sidewall spacers are etched away. The semiconductor substrate is sputter etched to round the corners of the trenches. An oxide trench lining layer is grown overlying the semiconductor substrate. A trench fill layer is deposited overlying the silicon nitride layer and filling the trenches. The trench fill layer is polished down to the top surface of the silicon nitride layer. The silicon nitride layer is etched away. The trench fill layer and the pad oxide layer are polished down to the top surface of the semiconductor substrate to complete the shallow trench isolation, and the integrated circuit device is completed.

Claims

1. A method for fabricating shallow trench isolations in the manufacture of an integrated circuit device comprising:

providing a semiconductor substrate;

growing a pad oxide layer overlying said semiconductor substrate;

depositing a silicon nitride layer overlying said pad oxide layer;

patterning said silicon nitride layer and said pad oxide layer to form a hard mask wherein openings in said hard mask correspond to planned trenches;

depositing a silicon dioxide layer overlying said silicon nitride layer and said semiconductor substrate;

anisotropically etching said silicon dioxide layer to form sidewall spacers on the inside of said openings in said hard mask;

thereafter etching said semiconductor substrate to form said trenches;

thereafter etching away said sidewall spacers;

thereafter rounding corners of said trenches by sputter etching said semiconductor substrate or by annealing said semiconductor substrate with hydrogen;

thereafter growing an oxide trench lining layer overlying said semiconductor substrate;

depositing a trench fill layer overlying said silicon nitride layer and said oxide trench lining layer and filling said trenches;

polishing down said trench fill layer to the top surface of said silicon nitride layer;

etching away said silicon nitride layer;

polishing down said trench fill layer and said pad oxide layer to the top surface of said semiconductor substrate to complete said shallow trench isolations; and

completing said integrated circuit device.

2. The method according to claim 1 wherein said silicon nitride layer is deposited to a thickness of between about 1,000 Angstroms and 2,000 Angstroms.

3. The method according to claim 1 wherein said silicon dioxide layer is deposited to a thickness of between about 500 Angstroms and 1,500 Angstroms.

4. The method according to claim 1 wherein said sidewall spacers are formed to a width of between about 300 microns and 1,000 microns.

5. The method according to claim 1 wherein said trench fill layer comprises silicon dioxide deposited to a thickness of between about 5,000 Angstroms and 9,000 Angstroms.

6. The method according to claim 1 wherein said oxide trench lining layer is deposited to a thickness of between about 100 Angstroms and 300 Angstroms.

7. A method for fabricating shallow trench isolations in the manufacture of an integrated circuit device comprising:

providing a semiconductor substrate;

growing a pad oxide layer overlying said semiconductor substrate;

depositing a silicon nitride layer overlying said pad oxide layer;

patterning said silicon nitride layer and said pad oxide layer to form a hard mask wherein openings in said hard mask correspond to planned trenches;

depositing a silicon dioxide layer overlying said silicon nitride layer and said semiconductor substrate;

anisotropically etching said silicon dioxide layer to form sidewall spacers on the inside of said openings in said hard mask;

thereafter etching said semiconductor substrate to form said trenches;

thereafter etching away said sidewall spacers;

thereafter sputter etching said semiconductor substrate to thereby round the corners of said trenches;

thereafter growing an oxide trench lining layer overlying said semiconductor substrate;

depositing a trench fill layer overlying said silicon nitride layer and said oxide trench lining layer and filling said trenches;

polishing down said trench fill layer to the top surface of said silicon nitride layer;

etching away said silicon nitride layer;

polishing down said trench fill layer and said pad oxide layer to the top surface of said semiconductor substrate to complete said shallow trench isolations; and

completing said integrated circuit device.

8. The method according to claim 7 wherein said silicon dioxide layer is deposited to a thickness of between about 500 Angstroms and 1,500 Angstroms.

9. The method according to claim 7 wherein said sidewall spacers are formed to a width of between about 300 microns and 1,000 microns.

10. The method according to claim 7 wherein said trench fill layer comprises silicon dioxide deposited to a thickness of between about 5,000 Angstroms and 9,000 Angstroms.

11. The method according to claim 7 wherein said oxide trench lining layer is deposited to a thickness of between about 100 Angstroms and 300 Angstroms.

12. The method according to claim 7 wherein said step of sputter etching said semiconductor substrate is by a plasma etching process with a chemistry comprising Cl₂, BCl₃, CCl₄, CHF₃, CF₄, and a combination of HBr, Cl₂, and O₂.

13. A method for fabricating shallow trench isolations in the manufacture of an integrated circuit device comprising:

providing a semiconductor substrate;

growing a pad oxide layer overlying said semiconductor substrate;

depositing a silicon nitride layer overlying said pad oxide layer;

patterning said silicon nitride layer and said pad oxide layer to form a hard mask wherein openings in said hard mask correspond to planned trenches;

depositing a silicon dioxide layer overlying said silicon nitride layer and said semiconductor substrate;

anisotropically etching said silicon dioxide layer to form sidewall spacers on the inside of said openings in said hard mask;

thereafter etching said semiconductor substrate to form said trenches;

thereafter etching away said sidewall spacers;

thereafter annealing said semiconductor substrate with hydrogen to thereby round the corners of said trenches;

thereafter growing an oxide trench lining layer overlying said semiconductor substrate;

depositing a trench fill layer overlying said silicon nitride layer and said oxide trench lining layer and filling said trenches;

polishing down said trench fill layer to the top surface of said silicon nitride layer;

etching away said silicon nitride layer;

polishing down said trench fill layer and said pad oxide layer to the top surface of said semiconductor substrate to complete said shallow trench isolations; and

completing said integrated circuit device.

14. The method according to claim 13 wherein said silicon dioxide layer is deposited to a thickness of between about 500 Angstroms and 1,500 Angstroms.

15. The method according to claim 13 wherein said sidewall spacers are formed to a width of between about 300 microns and 1,000 microns.

16. The method according to claim 13 wherein said trench fill layer comprises silicon dioxide deposited to a thickness of between about 5,000 Angstroms and 9,000 Angstroms.

17. The method according to claim 13 wherein said oxide trench lining layer is deposited to a thickness of between about 100 Angstroms and 300 Angstroms.

18. The method according to claim 13 wherein said step of annealing said semiconductor substrate with hydrogen to thereby round the corners of said trenches comprises:

an H₂ ambient with a temperature of between about 800 degrees C. and 1,200 degrees C. for between about 15 minutes and 60 minutes.