Method of forming an alloy precipitate to surround interconnect to minimize electromigration

• US 6,228,759 B1
• Filed: 05/02/2000
• Issued: 05/08/2001
• Est. Priority Date: 05/02/2000
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Wang, Pin-Chin C., Woo, Christy M., Lopatin, Sergey
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): GURLEY, LYNNE ANN
• Application Number:
  US09/561,622
• Time in Patent Office: 371 Days
• Field of Search: 438/625, 438/626, 438/627, 438/629, 438/633, 438/640, 438/643, 438/645, 438/648, 438/660, 438/687
• US Class Current: 438/625
• CPC Class Codes: H01L 21/2855 by physical means, e.g. sputtering, evaporation H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76867 characterized by methods of formation other than PVD, CVD or deposition from a liquids PVD H01L21/2855; CVD H01L21/28556; deposition from liquids H01L21/288
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76886 Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
• CPC Class Codes: H01L 2221/1089 Stacks of seed layers

Abstract

An alloy precipitate is formed to surround a conductive fill within an interconnect opening, including especially a top surface of the conductive fill, to prevent drift of material from the conductive fill into the insulating layer that is surrounding the interconnect opening. An alloy material is deposited non-conformally such that the alloy material is deposited substantially only toward a top of the sidewalls of an interconnect opening and substantially only toward a center of the bottom wall of the interconnect opening. The interconnect opening is filled with the conductive material by growing the conductive material from a seed layer of the conductive material to form a conductive fill of the conductive material within the interconnect opening. The semiconductor wafer is heated to anneal the conductive fill within the interconnect opening such that the conductive fill forms into a substantially single grain structure. During the thermal anneal, reactant within the alloy material migrates along a top surface of the conductive fill and along a grain boundary of the conductive fill. An alloy precipitate is formed from a reaction between the reactant and the conductive material at the top surface and at the grain boundary of the conductive fill when the semiconductor wafer is then cooled down. The alloy precipitate at the top surface and at the grain boundary of the conductive fill prevents drift of the conductive material along the top surface and along the grain boundary of the conductive fill and into the insulating layer surrounding the interconnect opening.

Claims

1. A method for filling an interconnect opening of an integrated circuit, said interconnect opening being within an insulating layer on a semiconductor wafer, the method including the steps of:

A. depositing a seed layer of a conductive material conformally onto sidewalls and a bottom wall of said interconnect opening;

B. depositing an alloy material non-conformally such that said alloy material is deposited substantially only toward a top of said sidewalls of said interconnect opening and substantially only toward a center of said bottom wall of said interconnect opening and such that said alloy material is substantially not deposited on any bottom corner of said interconnect opening;

C. filling said interconnect opening with said conductive material by growing said conductive material from any exposed surface of said seed layer of said conductive material to form a conductive fill of said conductive material within said interconnect opening;

D. heating said semiconductor wafer to anneal said conductive fill within said interconnect opening such that said conductive fill forms into a substantially single grain structure, and wherein said seed layer of said conductive material anneals into said substantially single grain structure of said conductive fill;

wherein a reactant within said alloy material migrates along a top surface of said conductive fill and along a grain boundary of said conductive fill when said semiconductor wafer is heated; and

E. forming an alloy precipitate from a reaction between said reactant and said conductive material on said top surface and at said grain boundary of said conductive fill when said semiconductor wafer is cooled down after said step D;

and wherein said alloy precipitate on said top surface and at said grain boundary of said conductive fill prevents drift of said conductive material along said top surface and said grain boundary of said conductive fill and into said insulating layer surrounding said interconnect opening.

2. The method of claim 1, wherein said step A of depositing said seed layer is performed before said step B of depositing said alloy material such that said alloy material is deposited on said seed layer.

3. The method of claim 1, wherein said step B of depositing said alloy material is performed before said step A of depositing said seed layer such that said seed layer is deposited on said alloy material.

4. The method of claim 1, further including the step of:

polishing said semiconductor wafer after said step C such that said alloy material and said conductive fill are contained within said interconnect opening;

wherein said alloy material toward said top of said sidewalls of said interconnect opening is exposed after polishing said semiconductor wafer.

5. The method of claim 4, wherein said step D of heating said semiconductor wafer includes a step of:

performing a first thermal anneal at a relatively high temperature above about 250°

Celsius for a time period in a range of from about 10 minutes to about 1 hour after said step of polishing said semiconductor wafer.

6. The method of claim 5, further including a step of:

performing a second thermal anneal at a relatively low temperature in a range of from about 100°

Celsius to about 250°

Celsius for a time period in a range of from about 10 minutes to about 1 hour before said step of polishing said semiconductor wafer.

7. The method of claim 1, wherein said step B of non-conformally depositing said alloy material is performed with a PVD (physical vapor deposition) process.

8. The method of claim 1, further including the step of:

depositing a diffusion barrier layer on said sidewalls and said bottom wall of said interconnect opening before said step A and said step B, wherein said diffusion barrier layer prevents diffusion of said conductive material of said conductive fill into said insulating layer surrounding said interconnect opening.

9. The method of claim 1, wherein said conductive material is copper and wherein said insulating layer surrounding said interconnect opening is comprised of silicon dioxide (SiO₂).

10. The method of claim 1, further including the step of:

depositing a capping layer over said interconnect opening, wherein said alloy precipitate at said top surface of said conductive fill prevents drift of said conductive material from said conductive fill along a bottom surface of said capping layer and into said insulating layer surrounding said interconnect opening.

11. The method of claim 10, wherein said conductive material is copper, and wherein said insulating layer surrounding said interconnect opening is comprised of silicon dioxide (SiO₂), and wherein said capping layer is comprised of silicon nitride (SiN).

12. The method of claim 1, wherein said conductive material is copper, and wherein said alloy material is one of copper tin or copper zirconium.

13. The method of claim 1, further including the step of:

rounding a top corner of said interconnect opening by sputtering insulating material of said insulating layer at said top corner of said interconnect opening before depositing any material within said interconnect opening.

14. A method for filling an interconnect opening of an integrated circuit with copper, said interconnect opening being within an insulating layer of silicon dioxide (SiO₂) on a silicon semiconductor wafer, the method including the steps of:

A. rounding a top corner of said interconnect opening by sputtering silicon dioxide of said insulating layer at said top corner of said interconnect opening;

B. depositing a diffusion barrier layer on sidewalls and a bottom wall of said interconnect opening, wherein said diffusion barrier layer prevents diffusion of copper to be filled within said interconnect opening into said insulating layer surrounding said interconnect opening;

C. depositing a seed layer of copper conformally onto said diffusion barrier layer on said sidewalls and said bottom wall of said interconnect opening;

D. depositing an alloy material non-conformally such that said alloy material is deposited on said seed layer substantially only toward a top of said sidewalls of said interconnect opening and substantially only toward a center of said bottom wall of said interconnect opening and such that said alloy material is substantially not deposited on any bottom corner of said interconnect opening, wherein said step D of non-conformally depositing said alloy material is performed with a PVD physical vapor deposition) process, and wherein said alloy material is one of copper tin or copper zirconium;

E. filling said interconnect opening with copper by growing copper from any exposed surface of said seed layer to form a conductive fill of copper within said interconnect opening;

F. heating said semiconductor wafer by performing a first thermal anneal at a relatively low temperature in a range of from about 100°

Celsius to about 250°

Celsius for a time period in a range of from about 10 minutes to about 1 hour;

G. polishing said semiconductor wafer such that said alloy material and said conductive fill are contained within said interconnect opening;

wherein said alloy material toward said top of said sidewalls of said interconnect opening is exposed after polishing said semiconductor wafer;

H. heating said semiconductor wafer by performing a second thermal anneal at a relatively high temperature above about 250°

Celsius for a time period in a range of from about 10 minutes to about 1 hour after said step of polishing said semiconductor wafer;

wherein said conductive fill forms into a substantially single grain structure, and wherein said seed layer of said conductive material incorporates into said substantially single grain structure of said conductive fill;

and wherein a reactant within said alloy material migrates along a top surface of said conductive fill and along a grain boundary of said conductive fill when said semiconductor wafer is heated;

I. forming an alloy precipitate from a reaction between said reactant and said conductive material on said top surface and at said grain boundary of said conductive fill when said semiconductor wafer is cooled down to room temperature after said step H; and

J. depositing a capping layer over said interconnect opening, wherein said capping layer is comprised of silicon nitride (SiN);

and wherein said alloy precipitate on said top surface and at said grain boundary of said conductive fill prevents drift of said conductive material along said top surface and said grain boundary of said conductive fill and into said insulating layer surrounding said interconnect opening;

and wherein said alloy precipitate on said top surface of said conductive fill prevents drift of said conductive material from said conductive fill along a bottom surface of said capping layer and into said insulating layer surrounding said interconnect opening.