Using cascaded gain stages for high-gain and high-speed readout of pixel sensor data

• US 6,229,134 B1
• Filed: 07/20/1999
• Issued: 05/08/2001
• Est. Priority Date: 10/13/1998
• Status: Expired due to Term

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Photobit Corporation (Micron Technology, Inc.)
• Inventors: Barna, Sandor L., Ang, Lin Ping
• Primary Examiner(s): Allen, Stephone B.
• Application Number:
  US09/357,605
• Time in Patent Office: 658 Days
• Field of Search: 250/208.1, 250/214.1, 250/214 R, 348/294, 348/297, 348/298, 348/300-303, 348/308, 348/311, 348/312, 358/482, 358/483, 257/443, 257/444, 257/290-292
• US Class Current: 250/208.1
• CPC Class Codes: H01L 27/14601 Structural or functional details thereof
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof

Abstract

A sampling and readout system including a cascaded stage charge amplifier samples, amplifies, and outputs pixel sensor data from an array of pixel sensors. The charge amplifier divides the gain into several gain stages. Each gain stage amplifies the pixel sensor data.

Claims

1. A pixel sensor readout system comprising:

a sampling circuitry configured to sequentially sample pixel sensor data from an array of pixel sensors, said pixel sensor data representing photons integrated as charge and collected by said pixel sensors;

a charge amplifier having at least two cascaded gain stages, the charge amplifier coupled to said sampling circuitry and configured to amplify the pixel sensor data in both of said cascaded gain stages; and

a readout circuitry coupled to said charge amplifier and configured to sequentially output an analog voltage corresponding to each of the amplified pixel sensor data.

2. The system of claim 1, wherein each gain stage of the charge amplifier has an input terminal and an output terminal and includes:

an op-amp having a positive and a negative inputs and an output, the op-amp configured to amplify a voltage present at the negative input with respect to some reference voltage at the positive input, and to drive the output with the amplified voltage;

a feedback capacitor connected between the output and the negative input of the op-amp; and

an input capacitor connected between the input terminal of the gain stage and the negative input of the op-amp, such that the gain of the op-amp is determined by the ratio of the value of the feedback capacitor and the input capacitor.

3. The system of claim 2, further comprising:

a reset switch connected between the output and the negative input of the op-amp, where the reset switch is configured to remain closed until a signal to initiate amplification operation opens the reset switch.

4. The system of claim 1, further comprising:

a source-follower buffer having an input and an output and placed between the gain stages, the input connected to a preceding gain stage and the output connected to a succeeding gain stage, where the buffer operates to isolate the high-resistance preceding gain stage from the low-resistance succeeding gain stage.

5. The system of claim 1, wherein the sampling circuitry includes two branches, each branch including:

a sampling switch to sample the pixel sensor data from an array of pixel sensors at a particular time, the sampling switches in the two branches operating sequentially to generate a difference voltage between the two sampled pixel sensor data, where the difference voltage represents a difference in the photon count collected by two branches at different times; and

a holding capacitor to store the sampled pixel sensor data.

6. The system of claim 5, wherein the sampling circuitry further includes:

a double sampling circuit configured to short the two sampled pixel sensor data present on the holding capacitors of the two branches to reduce noise in the sensor data.

7. The system of claim 5, wherein the array of pixel sensors are arranged in rows of columns, such that the sampling circuitry includes column selection switches to sample the pixel sensor data from sequential columns in a row.

8. The system of claim 7, wherein the readout circuitry is configured to be capable of addressing and reading out the pixel sensor data from any pixel sensor in the array of pixel sensors.

9. A charge amplifier for use in amplifying pixel sensor data from image sensors, the charge amplifier having a cascade of gain stages, each gain stage including:

an op-amp having a positive and a negative inputs and an output, the op-amp configured to amplify a voltage present at the negative input with respect to some reference voltage at the positive input, and to drive the output with the amplified voltage;

a feedback capacitor connected between the output and the negative input of the op-amp; and

an input capacitor connected between the input terminal of the gain stage and the negative input of the op-amp, such that the gain of the op-amp is determined by a ratio of the value of the feedback capacitor and the input capacitor.

10. The system of claim 9, further comprising:

a reset switch connected between the output and the negative input of the op-amp, where the reset switch is configured to remain closed until a signal to initiate amplification operation opens the reset switch.

11. An active pixel sensor system having an output port, the system comprising:

a pixel sensor array arranged in an array of rows and columns, the pixel sensor array configured to form an electrical representation of an image being sensed;

a row-select element coupled to the pixel sensor array and configured to select a row of pixel sensors;

a sampling and readout circuitry configured to sequentially sample sensor data from the pixel sensor array and output an analog voltage corresponding to each of the pixel sensor data, said sampling and readout circuitry including a charge amplifier having at least two cascaded gain stages, and a readout circuit coupled to the charge amplifier and configured to sequentially output an analog voltage; and

an analog-to-digital converter circuit configured to convert analog voltage outputted by the sampling and readout circuitry to digital pixel data, and to transfer the digital pixel data to the output port.

12. The system of claim 11, further comprising:

a timing and control unit coupled to the row-select element, the sampling and readout circuitry, and the analog-to-digital converter circuit, where the timing and control unit is configured to generate timing and control signals that select appropriate pixel data for sampling and transferring the data to the output port.

13. An active pixel sensor camera system for converting an array of pixel data to a visual image, the system comprising:

a pixel sensor array arranged in an array of rows and columns, the pixel sensor array configured to form an electrical representation of an image being sensed;

a row-select element coupled to the pixel sensor array and configured to select a row of pixel sensors;

a sampling and readout circuitry configured to sequentially sample sensor data from the pixel sensor array, and output an analog voltage corresponding to each of the pixel sensor data;

an analog-to-digital converter circuit configured to convert analog voltage outputted by the sampling and readout circuitry to digital pixel data, and to transfer the digital pixel data to the output port; and

an image display device coupled to the analog-to-digital converter circuit and having a display screen, the image display device configured to transfer pixel data from the output port, such that the device arranges the pixel data in sequential order of rows to display the visual image on the display screen.

14. The system of claim 13, wherein the sampling and readout circuitry includes:

a sampling circuitry configured to sequentially sample pixel sensor data from an array of pixel sensors, the pixel sensor data representing photons integrated as electrons and collected by the pixel sensors;

a charge amplifier having a cascade of gain stages, the charge amplifier coupled to the sampling circuitry and configured to amplify the pixel sensor data; and

a readout circuitry coupled to the charge amplifier and configured to sequentially output an analog voltage corresponding to each of the amplified pixel sensor data.

15. The system of claim 13, further comprising:

a timing and control unit coupled to the row-select element, the sampling and readout circuitry, and the analog-to-digital converter circuit, where the timing and control unit is configured to generate timing and control signals that select appropriate pixel data for sampling and transferring the data to the output port.