Semiconductor capacitively-coupled NDR device and its applications in high-density high-speed memories and in power switches
First Claim
1. A semiconductor device, comprising:
- an NDR device having end regions at either end of at least two contiguous regions of opposite polarity; and
a control port located adjacent to, capacitively coupled to and facing at least one of the regions of the NDR device, said one region having a cross-section along a plane facing an interface between two of said contiguous regions, the control port and the NDR device configured and arranged with the cross-section having thickness wherein the capacitive coupling between the gate and said one region changes the potential across a majority of the cross-section in response to at least one voltage transition presented to the control port and independent of any MOS inversion channel formation against said one region, and therein enhancing switching of the NDR device between a current-passing mode and a current-blocking mode for current between the end regions.
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Abstract
A novel capacitively coupled NDR device can be used to implement a variety of semiconductor circuits, including high-density SRAM cells and power thyristor structures. In one example embodiment, the NDR device is used as a thin vertical PNPN structure with capacitively-coupled gate-assisted turn-off and turn-on mechanisms. An SRAM based on this new device is comparable in cell area, standby current, architecture, speed, and fabrication process to a DRAM of the same capacity. In one embodiment, an NDR-based SRAM cell consists of only two elements, has an 8 F2 footprint, can operate at high speeds and low voltages, has a good noise-margin, and is compatible in fabrication process with main-stream CMOS. This cell significantly reduces standby power consumption compared to other types of NDR-based SRAMs.
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Citations
22 Claims
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1. A semiconductor device, comprising:
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an NDR device having end regions at either end of at least two contiguous regions of opposite polarity; and
a control port located adjacent to, capacitively coupled to and facing at least one of the regions of the NDR device, said one region having a cross-section along a plane facing an interface between two of said contiguous regions, the control port and the NDR device configured and arranged with the cross-section having thickness wherein the capacitive coupling between the gate and said one region changes the potential across a majority of the cross-section in response to at least one voltage transition presented to the control port and independent of any MOS inversion channel formation against said one region, and therein enhancing switching of the NDR device between a current-passing mode and a current-blocking mode for current between the end regions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 18, 19, 20, 21)
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8. A semiconductor device, comprising:
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current switching means, having an NDR device with at least two contiguous regions of opposite polarity, for passing or blocking current between opposite ends of the at least two contiguous regions, at least one of the regions of the current switching means having a cross-section along a plane facing an interface between two of said contiguous regions;
coupling means adjacent and facing at least one of the contiguous regions, for capacitively coupling a charge adjacent said one region, the control port and the current switching means configured and arranged with the cross-section having a thickness wherein the capacitive coupling between the gate and said one region changes the potential across the entire cross-section in response to at least one voltage transition presented to the charge-coupling mean and independent of any MOS inversion channel formation against said one region, and therein enhancing switching of the current switching means between a current-passing mode and a current-blocking mode. - View Dependent Claims (9, 10, 11, 12)
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13. A semiconductor device, comprising:
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an array of memory cells;
a data circuit configured and arranged to provide data for reading and writing to one or more selected cells in the array;
each cell having a storage node, a capacitively-switched NDR device have a capacitively-coupled control gate facing the NDR device, having end regions at either end of the NDR device, and being configured and arranged to enhance writing to the storage mode by enhancing switching of the NDR device between a current-passing mode and a current-blocking mode for current passing between the end regions, and an access circuit configured and arranged to couple data between the storage node and the data circuit. - View Dependent Claims (22)
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14. An SRAM device, comprising:
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a storage node;
a first sword line;
a second word line;
an NDR device including a capacitively-coupled gate configured and arranged to respond to the second word line; and
an access circuit having a control port coupled to the first word line and configured and arranged to couple data between the storage node and a bit line, the NDR device configured and arranged in a pedestal extending above the substrate, with the capacitively-coupled gate surrounding at least a portion of the pedestal.
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15. An SRAM device, comprising:
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a storage node;
a first word line;
a second word line;
a vertically-arranged NDR device including at least two contiguous stacked regions of opposite polarity, and including a gate having one side thereof capacitively-coupled to and facing at least one of the regions and configured and arranged to respond to the second word line by enhancing switching of the NDR device from a current-passing mode to a current-blocking mode; and
an access circuit having a control port coupled to the first word line and configured and arranged to couple data between the storage node and a bit line. - View Dependent Claims (16, 17)
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Specification