Semiconductor capacitively-coupled NDR device and its applications in high-density high-speed memories and in power switches

• US 6,229,161 B1
• Filed: 06/05/1998
• Issued: 05/08/2001
• Est. Priority Date: 06/05/1998
• Status: Expired due to Term

• Current Assignee: Stanford University
• Original Assignee: Stanford University
• Inventors: Nemati, Farid, Plummer, James D.
• Primary Examiner(s): CRANE, SARA W
• Application Number:
  US09/092,449
• Time in Patent Office: 1,068 Days
• Field of Search: 257/133, 257/138, 257/147, 257/148, 257/149, 257/150, 257/151, 257/153, 257/155, 257/167, 257/903, 365/180
• US Class Current: 257/133
• CPC Class Codes: G11C 11/39 using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT
• CPC Class Codes: H01L 27/0617 comprising components of the field-effect type H01L27/0251 takes precedence
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1027 Thyristors
• CPC Class Codes: H01L 29/41716 Cathode or anode electrodes for thyristors
• CPC Class Codes: H01L 29/42308 Gate electrodes for thyristors
• CPC Class Codes: H01L 29/74 Thyristor-type devices, e.g. having four-zone regenerative action two-terminal thyristors H01L29/87
• CPC Class Codes: H01L 29/749 with turn-on by field effect
• CPC Class Codes: H01L 29/87 Thyristor diodes, e.g. Shockley diodes, break-over diodes
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 12/10 DRAM devices comprising bipolar components

Abstract

A novel capacitively coupled NDR device can be used to implement a variety of semiconductor circuits, including high-density SRAM cells and power thyristor structures. In one example embodiment, the NDR device is used as a thin vertical PNPN structure with capacitively-coupled gate-assisted turn-off and turn-on mechanisms. An SRAM based on this new device is comparable in cell area, standby current, architecture, speed, and fabrication process to a DRAM of the same capacity. In one embodiment, an NDR-based SRAM cell consists of only two elements, has an 8 F² footprint, can operate at high speeds and low voltages, has a good noise-margin, and is compatible in fabrication process with main-stream CMOS. This cell significantly reduces standby power consumption compared to other types of NDR-based SRAMs.

Claims

1. A semiconductor device, comprising:

an NDR device having end regions at either end of at least two contiguous regions of opposite polarity; and

a control port located adjacent to, capacitively coupled to and facing at least one of the regions of the NDR device, said one region having a cross-section along a plane facing an interface between two of said contiguous regions, the control port and the NDR device configured and arranged with the cross-section having thickness wherein the capacitive coupling between the gate and said one region changes the potential across a majority of the cross-section in response to at least one voltage transition presented to the control port and independent of any MOS inversion channel formation against said one region, and therein enhancing switching of the NDR device between a current-passing mode and a current-blocking mode for current between the end regions.

2. A semiconductor device, according to claim 1, wherein the NDR device is a PNPN device.

3. A semiconductor device, according to claim 1, wherein the control port and the NDR device are further configured and arranged so that, in response to the voltage transition presented to the control port, the potential across the entire cross-section is changeable by the outflow of excess charges from said one region.

4. A semiconductor device, according to claim 1, further including at least one other NDR device having at least two contiguous regions of opposite polarity;

and another control port located adjacent to and facing at least one of the regions of the one other NDR device.

5. A semiconductor device, according to claim 4, wherein the first-mentioned NDR device and the first-mentioned control port and the other NDR device and the other control port form part of a semiconductor power switch.

6. A semiconductor device, according to claim 1, further including an array of memory cells and wherein the NDR device and the control port are components in one memory cell forming part of the array.

7. A semiconductor device, according to claim 6, wherein the one memory cell forming part of the array includes a storage node and an access circuit configured and arranged to provide access to the storage node;

and wherein the control port is configured and arranged to enhance writing access to the storage node.

18. A semiconductor device, according to claim 1, wherein the NDR device is a PNPN device.

19. The semiconductor device of claim 1, wherein said at least one voltage transition enhances switching of the NDR device from the current-blocking mode to the current-passing mode.

20. The semiconductor device of claim 1, wherein said at least one voltage transition enhances switching of the NDR device from the current-blocking mode to the current-passing mode and from the current-passing mode to the current-blocking mode.

21. The semiconductor device of claim 1, wherein the NDR device does not include a MOS-controlled thyristor.

8. A semiconductor device, comprising:

current switching means, having an NDR device with at least two contiguous regions of opposite polarity, for passing or blocking current between opposite ends of the at least two contiguous regions, at least one of the regions of the current switching means having a cross-section along a plane facing an interface between two of said contiguous regions;

coupling means adjacent and facing at least one of the contiguous regions, for capacitively coupling a charge adjacent said one region, the control port and the current switching means configured and arranged with the cross-section having a thickness wherein the capacitive coupling between the gate and said one region changes the potential across the entire cross-section in response to at least one voltage transition presented to the charge-coupling mean and independent of any MOS inversion channel formation against said one region, and therein enhancing switching of the current switching means between a current-passing mode and a current-blocking mode.

9. A semiconductor device, according to claim 8, further including at least one other similar-functioning current switching means and at least one other similar-functioning coupling means.

10. A semiconductor device, according to claim 9, wherein each of the coupling means and each of the current switching means form part of a semiconductor power switch.

11. A semiconductor device, according to claim 8, further including an array of memory cells;

and wherein the current switching means and the coupling means are components in one memory cell forming part of the array.

12. A semiconductor device, according to claim 11, wherein the one memory cell forming part of the array includes a storage node and an access circuit configured and arranged to provide access lo the storage node, and wherein the coupling means is configured and arranged to enhance writing access to the storage node.

13. A semiconductor device, comprising:

an array of memory cells;

a data circuit configured and arranged to provide data for reading and writing to one or more selected cells in the array;

each cell having a storage node, a capacitively-switched NDR device have a capacitively-coupled control gate facing the NDR device, having end regions at either end of the NDR device, and being configured and arranged to enhance writing to the storage mode by enhancing switching of the NDR device between a current-passing mode and a current-blocking mode for current passing between the end regions, and an access circuit configured and arranged to couple data between the storage node and the data circuit.

22. The semiconductor device of claim 13, wherein the NDR device does not include a MOS-controlled thyristor.

14. An SRAM device, comprising:

a storage node;

a first sword line;

a second word line;

an NDR device including a capacitively-coupled gate configured and arranged to respond to the second word line; and

an access circuit having a control port coupled to the first word line and configured and arranged to couple data between the storage node and a bit line, the NDR device configured and arranged in a pedestal extending above the substrate, with the capacitively-coupled gate surrounding at least a portion of the pedestal.

15. An SRAM device, comprising:

a storage node;

a first word line;

a second word line;

a vertically-arranged NDR device including at least two contiguous stacked regions of opposite polarity, and including a gate having one side thereof capacitively-coupled to and facing at least one of the regions and configured and arranged to respond to the second word line by enhancing switching of the NDR device from a current-passing mode to a current-blocking mode; and

an access circuit having a control port coupled to the first word line and configured and arranged to couple data between the storage node and a bit line.

16. An SRAM device, according to claim 15, wherein said one region has a cross-section along a plane facing an interface between two of said contiguous regions, the gate and the NDR device configured and arranged so that the potential across the entire cross-section changes in response to a control voltage presented to the gate and therein enhances switching of the NDR circuit between a current passing mode and a current blocking mode.

17. An SRAM device, according to claim 16, wherein the NDR device is a PNPN device.