Method and apparatus for generating a time delayed signal with a minimum data dependency error using an oscillator

• US 6,229,367 B1
• Filed: 08/02/1999
• Issued: 05/08/2001
• Est. Priority Date: 06/26/1997
• Status: Expired due to Term

• Current Assignee: Microsemi Storage Solutions, Inc (Microchip Technology Incorporated)
• Original Assignee: Vitesse Semiconductor Corp (Microchip Technology Incorporated)
• Inventors: Choudhury, Ashish K.
• Primary Examiner(s): Lam, Tuan T.
• Application Number:
  US09/365,189
• Time in Patent Office: 645 Days
• Field of Search: 327/276, 327/277, 327/261, 327/262, 327/263, 327/269, 327/270, 327/291, 327/292, 327/299
• US Class Current: 327/276
• CPC Class Codes: G01R 31/31922 Timing generation or clock distribution G01R31/3191 takes precedence
• CPC Class Codes: H03K 2005/00241 using shift registers
• CPC Class Codes: H03K 5/13 Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
• CPC Class Codes: H03K 5/131 Digitally controlled
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03K 5/135 by the use of time reference signals, e.g. clock signals

Abstract

The present invention provides a time delay system that generates a selectable asynchronous time delayed signal from an incoming signal using a pulse having a minimum pulse width and stop-startable oscillator. The time delay system of the present invention produces a minimum data dependency error which is independent of the repetition rate of the incoming signal, the substrate settling time, and the length of the time delay of the delayed signal.

Claims

1. An apparatus used in generating a delayed output signal from an input signal, comprising:

an oscillator generating an oscillating signal, the oscillator including a substrate, the substrate having a substrate settling time;

a pulse generator coupled to said oscillator, said pulse generator generating a first delayed signal in response to said input signal, the first delayed signal having a leading edge and a trailing edge, said leading edge of said first delayed signal stops oscillating signal and said trailing edge restarts said oscillating signal, with said leading edge and said trailing edge separated in time by less than the substrate settling time.

2. The apparatus of claim 1, wherein said oscillator generates a plurality of oscillating signals that are stopped and re-started by said first delayed signal,

said apparatus further comprising:

a phase selector selecting one of said plurality of oscillating signals.

3. The apparatus of claim 2 further comprising:

a vernier coupled to said phase selector, said vernier delaying said selected one of said plurality of oscillating signals.

4. The apparatus of claim 3 further comprising:

a shift register coupled to said pulse generator, said shift register receiving the first delayed signal as a data input and receiving the selected one of said plurality of oscillating signals delayed by the vernier as a clock input, the shift register outputting the delayed output signal.

5. The apparatus of claim 3 wherein the vernier comprises a signal line receiving the selected one of the said plurality of oscillating signals, a plurality of capacitors operably coupled to the signal line by a plurality of switches, each of the plurality of capacitors having an associated switch of the plurality of switches.

6. The apparatus of claim 5 wherein the vernier further comprises decode logic, the decode logic providing signals to control inputs of the plurality of switches.

7. The apparatus of claim 4 further comprising a pipeline, the pipeline passing the first delayed signal from the pulse generator to the shift register, the pipeline delaying the first delayed signal based upon which of the plurality of oscillating signals is selected.

8. An apparatus for generating a delayed output signal from an input signal comprising:

an oscillator generating a plurality of oscillating signals phase-shifted with respect to each other, the plurality of oscillating signals including at least one oscillating signal;

a pulse generator, coupled to said oscillator, said pulse generator generating a first delayed signal having a first time delay in response to said input signal, said first delayed signal stopping and re-starting said at least one oscillating signal,

a phase selector selecting one of said plurality of oscillating signals;

a vernier coupled to said phase selector, said vernier generating multiple steps of a second time delay for said delayed output signal;

a pipeline unit coupled to said pulse generator, said pipeline unit generating a second delayed signal from said first delayed signal; and

a register coupled to said pipeline and vernier, said register generating multiple steps of a third time delay for said delayed output signal, said register for outputting said delayed output signal in response to said second delayed signal and an output signal from said vernier.

9. The apparatus of claim 8, wherein said pipeline unit comprises:

a flip-flop coupled to said pulse generator;

a first buffer coupled to said flip-flop;

a second buffer coupled to said flip-flop;

a third buffer coupled to said second buffer;

a multiplexer coupled to said first and third buffers and to said register; and

an inverter coupled to said flip-flop and multiplexer.

10. The apparatus of claim 8, wherein said register comprises:

a de-multiplexer coupled to said pipeline unit; and

a plurality of flip-flops,

wherein said plurality of flip-flops are connected in series,

wherein all of said plurality of flip-flops except the last one in the series are directly coupled to said de-multiplexer.

11. The apparatus of claim 8, wherein each of the plurality of oscillating signals have substantially the same period and a step of said first time delay is between zero and one half period of the oscillating signals;

wherein a step of said second time delay is equal to or less than said step of said first time delay,

wherein a step of said third time delay is zero or is equal to one period of said oscillating signals, and

wherein a total selected time delay of said delayed output signal includes a sum of said first, second, and third time delays.

12. An apparatus for generating a delayed output signal from an input signal, comprising:

means for generating a plurality of oscillating signals, the plurality of oscillating signals including at least one oscillating signal; and

means for generating a first delayed signal having a first time delay in response to said input signal

wherein said plurality of oscillating signals have substantially the same period and are phase-shifted with respect to each other;

means for selecting one of said plurality of oscillating signals;

means for generating multiple steps of a second time delay for said delayed output signal;

means for generating a second delayed signal from said first delayed signal; and

means for generating multiple steps of a third time delay for said delayed output signal and for outputting said delayed output signal in response to said second delayed signal and an output from said means for generating said multiple steps of said second time delay,

wherein said means for generating said second delayed signal includes means for delivering said second delayed signal to said means for generating said multiple steps of said third time delay at a time appropriate for the amount of said first, second, and third time delays.

13. The apparatus of claim 12, wherein a step of said first time delay is between zero and one half period of said at least one oscillating signal,

wherein a step of said second time delay is equal to or less than said step of said first time delay,

wherein a step of said third time delay is zero or is equal to one period of said at least one oscillating signal, and

wherein a total selected time delay of said delayed output signal includes a sum of said first, second, and third time delays.

14. A method for generating a delayed output signal from an input signal, comprising:

generating a plurality of oscillating signals;

stopping said plurality of oscillating signals in response to a first edge of the input signal;

restarting said plurality of oscillating signals in response to second edge of the input signal;

selecting a one of the plurality of oscillating signals, the one of the plurality of oscillating signals forming a first delayed signal;

delaying the one of the plurality of oscillating signals by a small amount to form a second delayed signal; and

delaying the input signal, using the second delayed signal, to form the delayed output signal.

15. The method of claim 14 wherein delaying the input signal, using the second delayed signal, to form the delayed output signal comprises providing the input signal to a shift register the shift register being clocked by the second delayed signal.

16. The method of claim 15 wherein delaying the one of the plurality of oscillating signals by a small amount to form a second delayed signal comprises passing the one of the plurality of oscillating signals through a line coupled to a plurality of incremental capacitors.