Intelligent transceiver module particularly suited for power line control systems

• US 6,229,432 B1
• Filed: 10/30/1998
• Issued: 05/08/2001
• Est. Priority Date: 10/30/1997
• Status: Expired due to Fees

• Current Assignee: Advanced Control Technologies Inc.
• Original Assignee: Advanced Control Technologies Inc.
• Inventors: Shelow, Kevin J., Coffee, Curtis L., Fridley, Duane Patrick
• Primary Examiner(s): POPE, DARYL C
• Application Number:
  US09/183,708
• Time in Patent Office: 921 Days
• Field of Search: 340/506, 340/531, 340/532, 340/533, 340/534, 340/538, 340/825.06, 340/310.02, 340/310.04, 340/310.06, 340/310.01
• US Class Current: 340/12.35
• CPC Class Codes: H04B 2203/542 using zero crossing information
• CPC Class Codes: H04B 2203/5425 improving S/N by matching impedance, noise reduction, gain control
• CPC Class Codes: H04B 2203/5445 Local network
• CPC Class Codes: H04B 2203/5458 Monitor sensor; Alarm systems
• CPC Class Codes: H04B 2203/5483 using coupling circuits
• CPC Class Codes: H04B 2203/5491 using filtering and bypassing
• CPC Class Codes: H04B 3/542 the information being in digital form
• CPC Class Codes: H04B 3/546 Combination of signalling, telemetering, protection circuits for remote indication of supply or distribution network condition H02J13/00

Abstract

The present invention involves a module on a single board for a power line control system including a transmitter circuit, a receiver circuit, and a control circuit. The transmitter circuit sends signals over the power line. The receiver circuit receives signals sent over the power line. The control circuit couples to the transmitter circuitry and the receiver circuitry. The control circuit includes a microprocessor and associated memory. The memory includes instructions enabling the microprocessor to interpret the received signals, generate transmit signals, and control the circuit which controls the electrical appliance. The receiver circuit includes feedback for attenuating the input signal to the receiver circuit. The microprocessor includes an output signal for attenuating the input signal to the receiver circuit. The memory includes programmable memory which can be FLASH memory. The memory also includes serial EEPROM. The control circuit includes a low voltage reset for automatically resetting the microprocessor after a low voltage condition. The transmitter circuit provides a 6 volts peak to peak signal on a 5 ohm reactance loaded power line. The receiver circuit provides a minimum sensitivity of 25 mv over a loaded power line. The memory includes instructions for sending an automatic acknowledge upon receiving a valid signal. The instructions also include instructions for determining a start code by comparing bit count values for four consecutive bits.

Claims

1. A module for power line control systems to enhance electrical appliance control on a single board, said single board comprising:

a transmitter circuit for sending signals over a power line;

a receiver circuit for receiving signals transmitted over the power line; and

a control circuit coupled to said transmitting circuit and said receiving circuit, said control circuit including a microprocessor, a signal attenuation control circuit coupled to said receiver circuit, said signal attenuation circuit including a zero crossing detect circuit coupled to said microprocessor, said signal attenuation circuit structured and arranged to vary the amount of attenuation in relation to a count of complement pair signal pulses received by said receiver circuit, and associated memory, said memory including instructions enabling said microprocessor to interpret the conditioned received signals, generate transmit signals, attenuate the received signals according to the complement pair signal pulses counted by said microprocessor within a receive window of approximately one millisecond following a zero crossing detect, and control a circuit which controls the electrical appliance.

2. The module of claim 1 wherein said receiver circuit includes an input signal and an output signal, said output signal of said receiver circuit controlling said signal attenuation control circuit to attenuate said input signal of said receiver circuit.

3. The module of claim 1 wherein said microprocessor includes an output signal, said output signal of said microprocessor controlling said signal attenuation control circuit to attenuate said input signal of said receiver circuit.

4.The module of claim 1 wherein said memory includes programmable memory.

5. The module of claim 1 wherein said instructions include instructions for enabling said microprocessor to be responsive to an X-10 protocol including in sequence a four bit start code, a four bit address code and a five bit extended code command.

6. The module of claim 1 wherein said memory includes serial EEPROM.

7. The module of claim 1 wherein said control circuit includes a low voltage reset means for automatically resetting said microprocessor after a low voltage condition.

8. The module of claim 1 wherein said transmitter circuit includes means for providing a 6 volts peak to peak signal on a 5 ohm reactance loaded power line.

9. The module of claim 1 wherein said receiver circuit includes means for providing a minimum receiver sensitivity of 25 mV over a loaded power line.

10. The module of claim 1 wherein said memory includes instructions for sending an automatic acknowledgment upon receiving a valid signal.

11. The module of claim 1 wherein said instructions include instructions for determining a start code by comparing bit count values for four consecutive bits and determining address and command codes by comparing bit count values for two consecutive bits.

12. The module of claim 1 wherein said signal attenuation control circuit includes an attenuation control transistor coupled to said receiver circuit and a gate control voltage capacitor.

13. The module of claim 1 wherein said control circuit includes a switching transistor coupled to said gate control voltage capacitor of said signal attenuation control circuit and providing control of said signal attenuation control circuit.

14. The module of claim 1 wherein said signal attenuation control circuit coupled to said receiver circuit provides no attenuation with an input of 5 volts and total attenuation with an input of 0 volts from said microprocessor.

15. The module of claim 1 wherein said memory includes automatic level control instructions enabling microprocessor to control said signal attenuation control circuit.

19. The module of claim 1 wherein said single board is no greater in size than 4 inches by 2 inches by 2 inches.

20. The module of claim 12 wherein said bit count value for fourth bit of said four consecutive bits must be at least a predetermined value less than said bit counts for other bits of said four consecutive bits to determine said start code and said bit count values for said two consecutive bits must be different by at least said predetermined value to determine said command code.

4. The module of claim 4 wherein said programmable memory includes FLASH memory.

16. The module of claim 16 wherein said automatic level control instructions include pulse width modulation instructions enabling said microprocessor to provide a pulse width modulated signal to said signal attenuation control circuit.

17. The module of claim 16 wherein said microprocessor includes an input signal of pulses per cycle and said automatic level control instructions include pulse count instructions enabling said microprocessor to control said signal attenuation control circuit depending on the number of said pulses per cycle.

18. The module of claim 16 wherein said automatic level control instructions include instructions for comparing bit count values from alternating cycles and determining a differential enabling said microprocessor to control said signal attenuation control circuit depending on said differential.

21. A power line control system comprising:

a power line of the building;

a plurality of power outlets coupled to said line;

a master control unit coupled to said line;

a transceiver unit coupled to one of said power outlets, said unit comprising;

a module constructed on a single board comprising a transmitter circuit for sending signals over said line, a receiver circuit for receiving signals over said line, and a control circuit coupled to said transmitter circuit and receiver circuit, said control circuit including a microprocessor, a signal attenuation control circuit coupled to said receiver circuit, said signal attenuation circuit including a zero crossing detect circuit coupled to said microprocessor, said signal attenuation circuit structured and arranged to vary the amount of attenuation in relation to the signals received by said receiver circuit, and associated memory, said memory including instructions enabling said microprocessor to interpret the conditioned received signals, generate transmit signals, attenuate the received signals, and control a circuit which controls the electrical appliance; and

electrical appliance control circuitry coupled to said module; and

an electrical appliance coupled to said transceiver unit.

22. The system of claim 22 wherein said receiver circuit includes an input signal and an output signal, said output signal of said receiver circuit controlling said signal attenuation control circuit to attenuate said input signal of said receiver circuit.

23. The system of claim 22 wherein said microprocessor includes an output signal, said output signal of said microprocessor controlling said signal attenuation control circuit to attenuate said input signal of said receiver circuit.

24. The system of claim 22 wherein said memory includes programmable memory.

26. The system of claim 22 wherein said instructions include instructions for enabling said microprocessor to be responsive to an X-10 protocol including in sequence a four bit start code, a four bit address code and a five bit extended code command.

27. The system of claim 22 wherein said memory includes serial EEPROM.

28. The system of claim 22 wherein said control circuit includes a low voltage reset means for automatically resetting said microprocessor after a low voltage condition.

29. The system of claim 22 wherein said transmitter circuit includes means for providing a 6 volts peak to peak signal on a 5 ohm reactance loaded power line.

30. The system of claim 22 wherein said receiver circuit includes means for providing a minimum receiver sensitivity of 25 mV over a loaded power line.

31. The system of claim 22 wherein said memory includes instructions for sending an automatic acknowledgment upon receiving a valid signal.

32. The system of claim 22 wherein said transceiver unit a power input circuit coupled to one of said power outlets of said line.

33. The system of claim 22 wherein said master control unit includes means for transmitting a start code and said instructions include instructions for determining said start code by comparing bit count values for four consecutive bits and determining address and command codes by comparing bit count values for two consecutive bits.

34. The system of claim 22 wherein said signal attenuation control circuit includes an attenuation control transistor coupled to said receiver circuit and a gate control voltage capacitor.

36. The system of claim 22 wherein said signal attenuation control circuit coupled to said receiver circuit provides no attenuation with an input of 5 volts and total attenuation with an input of 0 volts from said microprocessor.

37. The system of claim 22 wherein said memory includes automatic level control instructions enabling microprocessor to control said signal attenuation control circuit.

41. The system of claim 22 wherein said transceiver unit is no greater in size than 4 inches by 2 inches by 2 inches.

42. The system of claim 34 wherein said bit count value for fourth bit of said four consecutive bits must be at least a predetermined value less than said bit counts for other bits of said four consecutive bits to determine said start code and said bit count values for said two consecutive bits must be different by at least said predetermined value to determine said command code.

25. The system of claim 25 wherein said programmable memory includes FLASH memory.

35. The system of claim 35 wherein said control circuit includes a switching transistor coupled to said gate control voltage capacitor of said signal attenuation control circuit and providing control of said signal attenuation control circuit.

38. The system of claim 38 wherein said automatic level control instructions include pulse width modulation instructions enabling said microprocessor to provide a pulse width modulated signal to said signal attenuation control circuit.

39. The system of claim 38 wherein said microprocessor includes an input signal of pulses per cycle and said automatic level control instructions include pulse count instructions enabling said microprocessor to control said signal attenuation control circuit depending on the number of said pulses per cycle.

40. The system of claim 38 wherein said automatic level control instructions include instructions for comparing bit count values from alternating cycles and determining a differential enabling said microprocessor to control said signal attenuation control circuit depending on said differential.

43. A transceiver unit for a power line control system, said transceiver unit comprising:

a power input circuit adapted to be coupled to a power line associated with the power line control system;

a module coupled to said power input circuit, said module constructed on a single board comprising a transmitter circuit for sending signals over the power line, a receiver circuit for receiving signals over the power line, and a control circuit coupled to said transmitter circuit and receiver circuit, said control circuit including a microprocessor and associated memory, said control circuit also included an attenuation circuit coupled to said receiver circuit, said signal attenuation circuit including a zero crossing detect circuit coupled to said microprocessor, said signal attenuation circuit structured and arranged to vary the amount of attenuation in relation to a count of complement pair signal pulses received by said receiver circuit, said memory including instructions enabling said microprocessor to interpret the conditioned and attenuated received signals, according to the complement pair signal pulses counted by said microprocessor within a receive window of approximately one millisecond following a zero crossing detect, and generate control signals, which control an electrical appliance; and

electrical appliance control circuitry coupled to said module and adapted to transmit said control signals to an electrical appliance;

said transceiver unit being no greater in size than 4 inches by 2 inches by 2 inches.

44. The transceiver unit of claim 44 wherein said receiver circuit includes an input signal and an output signal, said output signal of said receiver circuit controlling said signal attenuation control circuit to attenuate said input signal of said receiver circuit.

45. The transceiver unit of claim 44 wherein said microprocessor includes an output signal, said output signal of said microprocessor controlling said signal attenuation control circuit to attenuate said input signal of said receiver circuit.

46. The transceiver unit of claim 44 wherein said memory includes programmable memory.

47. The transceiver unit of claim 44 wherein said programmable memory includes FLASH memory.

48. The transceiver unit of claim 44 wherein said instructions include instructions for enabling said microprocessor to be responsive to an X-10 protocol including in sequence a four bit start code, a four bit address code and a five bit extended code command.

49. The transceiver unit of claim 44 wherein said memory includes serial EEPROM.

50. The transceiver unit of claim 44 wherein said control circuit includes a low voltage reset means for automatically resetting said microprocessor after a low voltage condition.

51. The transceiver unit of claim 44 wherein said transmitter circuit includes means for providing a 6 volts peak to peak signal on a 5 ohm reactance loaded power line.

52. The transceiver unit of claim 44 wherein said receiver circuit includes means for providing a minimum receiver sensitivity of 25 mV over a loaded power line.

53. The transceiver unit of claim 44 wherein said memory includes instructions for sending an automatic acknowledgment upon receiving a valid signal.

54. The transceiver unit of claim 44 wherein said instructions include instructions for determining a start code by comparing bit count values for four consecutive bits and determining address and command codes by comparing bit count values for two consecutive bits.

55. The transceiver unit of claim 44 wherein said control circuit includes a signal attenuation control circuit and said memory includes signal attenuation instructions enabling said microprocessor to attenuate the received signals.

63. The transceiver unit of claim 55 wherein said bit count value for fourth bit of said four consecutive bits must be at least a predetermined value less than said bit counts for other bits of said four consecutive bits to determine said start code and said bit count values for said two consecutive bits must be different by at least said predetermined value to determine said command code.

56. The transceiver unit of claim 56 wherein said signal attenuation control circuit includes an attenuation control transistor coupled to said receiver circuit and a gate control voltage capacitor.

58. The transceiver unit of claim 56 wherein said signal attenuation control circuit coupled to said receiver circuit provides no attenuation with an input of 5 volts and total attenuation with an input of 0 volts from said microprocessor.

59. The transceiver unit of claim 56 wherein said memory includes automatic level control instructions enabling microprocessor to control said signal attenuation control circuit.

57. The transceiver unit of claim 57 wherein said control circuit includes a switching transistor coupled to said gate control voltage capacitor of said signal attenuation control circuit and providing control of said signal attenuation control circuit.

60. The transceiver unit of claim 60 wherein said automatic level control instructions include pulse width modulation instructions enabling said microprocessor to provide a pulse width modulated signal to said signal attenuation control circuit.

61. The transceiver unit of claim 60 wherein said microprocessor includes an input signal of pulses per cycle and said automatic level control instructions include pulse count instructions enabling said microprocessor to control said signal attenuation control circuit depending on the number of said pulses per cycle.

62. The transceiver unit of claim 60 wherein said automatic level control instructions include instructions for comparing bit count values from alternating cycles and determining a differential enabling said microprocessor to control said signal attenuation control circuit depending on said differential.

64. A transceiver unit for a power line control system, said transceiver unit comprising:

a power input circuit adapted to be coupled to a power line associated with the power line control system;

a module coupled to said power input circuit, said module constructed on a single board comprising a transmitter circuit for sending signals over the power line, a receiver circuit for receiving signals over the power line, and a control circuit coupled to said transmitter circuit and receiver circuit, said control circuit including a microprocessor and associated memory, said memory including instructions enabling said microprocessor to interpret the conditioned received signals and generate control signals, said signals adapted to control an electrical appliance; and

electrical appliance control circuitry coupled to said module and located on said module, said electrical appliance control circuitry adapted to transmit said control signals to an electrical appliance, and including a signal attenuation circuit coupled to said receiver circuit, said signal attenuation circuit including a zero crossing detect circuit coupled to said microprocessor, said signal attenuation circuit structured and arranged to vary the amount of attenuation in relation to a count of complement pair signal pulses received by said receiver circuit within a receive window of approximately one millisecond following a zero crossing detect, said microprocessor instructions enabling said microprocessor to vary the attenuation according to the complement pair signal pulses counted by said microprocessor turning the electrical appliance on and off.

65. The transceiver unit of claim 65 wherein said control circuit includes a signal attenuation control circuit coupled to said receiver circuit and said receiver circuit includes an input signal and an output signal, said output signal of said receiver circuit controlling said signal attenuation control circuit to attenuate said input signal of said receiver circuit.

66. The transceiver unit of claim 65 wherein said control circuit includes a signal attenuation control circuit coupled to said receiver circuit and said microprocessor includes an output signal, said output signal of said microprocessor controlling said signal attenuation control circuit to attenuate said input signal of said receiver circuit.

67. The transceiver unit of claim 65 wherein said memory includes programmable memory.

69. The transceiver unit of claim 65 wherein said instructions include instructions for enabling said microprocessor to be responsive to an X-10 protocol including in sequence a four bit start code, a four bit address code and a five bit extended code command.

70. The transceiver unit of claim 65 wherein said memory includes serial EEPROM.

71. The transceiver unit of claim 65 wherein said control circuit includes a low voltage reset means for automatically resetting said microprocessor after a low voltage condition.

72. The transceiver unit of claim 65 wherein said transmitter circuit includes means for providing a 6 volts peak to peak signal on a 5 ohm reactance loaded power line.

73. The transceiver unit of claim 65 wherein said receiver circuit includes means for providing a minimum receiver sensitivity of 25 mV over a loaded power line.

74. The transceiver unit of claim 65 wherein said memory includes instructions for sending an automatic acknowledgment upon receiving a valid signal.

75. The transceiver unit of claim 65 wherein said instructions include instructions for determining a start code by comparing bit count values for four consecutive bits and determining address and command codes by comparing bit count values for two consecutive bits.

76. The transceiver unit of claim 65 wherein said control circuit includes a signal attenuation control circuit and said memory includes signal attenuation instructions enabling said microprocessor to attenuate the received signals.

84. The transceiver unit of claim 65 wherein said transceiver unit is no greater in size than 4 inches by 2 inches by 2 inches.

85. The transceiver unit of claim 76 wherein said bit count value for fourth bit of said four consecutive bits must be at least a predetermined value less than said bit counts for other bits of said four consecutive bits to determine said start code and said bit count values for said two consecutive bits must be different by at least said predetermined value to determine said command code.

68. The transceiver unit of claim 68 wherein said programmable memory includes FLASH memory.

77. The transceiver unit of claim 77 wherein said signal attenuation control circuit includes an attenuation control transistor coupled to said receiver circuit and a gate control voltage capacitor.

79. The transceiver unit of claim 77 wherein said signal attenuation control circuit coupled to said receiver circuit provides no attenuation with an input of 5 volts and total attenuation with an input of 0 volts from said microprocessor.

80. The transceiver unit of claim 77 wherein said memory includes automatic level control instructions enabling microprocessor to control said signal attenuation control circuit.

82. The transceiver unit of claim 77 wherein said microprocessor includes an input signal of pulses per cycle and said automatic level control instructions include pulse count instructions enabling said microprocessor to control said signal attenuation control circuit depending on the number of said pulses per cycle.

83. The transceiver unit of claim 77 wherein said automatic level control instructions include instructions for comparing bit count values from alternating cycles and determining a differential enabling said microprocessor to control said signal attenuation control circuit depending on said differential.

78. The transceiver unit of claim 78 wherein said control circuit includes a switching transistor coupled to said gate control voltage capacitor of said signal attenuation control circuit and providing control of said signal attenuation control circuit.

81. The transceiver unit of claim 81 wherein said automatic level control instructions include pulse width modulation instructs enabling said microprocessor to provide a pulse width modulated signal to said signal attenuation control circuit.