Active matrix light emitting diode pixel structure and concomitant method

• US 6,229,506 B1
• Filed: 04/22/1998
• Issued: 05/08/2001
• Est. Priority Date: 04/23/1997
• Status: Expired due to Term

• Current Assignee: MEC Management, LLC (Three Affiliated Tribes of the Fort Berthold Reservation, North Dakota)
• Original Assignee: Sarnoff Corporation (SRI International, Inc.)
• Inventors: Hsu, James Ya-Kong, Stewart, Roger Green, Hsueh, Fu-Lung, Kane, Michael Gillis, Dawson, Robin Mark Adrian, Ipri, Alfred Charles
• Primary Examiner(s): CHOW, DOON Y
• Application Number:
  US09/064,696
• Time in Patent Office: 1,112 Days
• Field of Search: 345/82, 345/92, 345/76, 345/46, 345/83, 315/169.4, 315/169.1, 315/169.3, 340/815.45
• US Class Current: 345/82
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0852 being a dynamic memory with more than one capacitor
• CPC Class Codes: G09G 2300/0861 with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
• CPC Class Codes: G09G 2320/02 Improving the quality of display appearance
• CPC Class Codes: G09G 2320/043 Preventing or counteracting the effects of ageing
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/325 the data current flowing through the driving transistor during a setting phase, e.g. by using a switch for connecting the driving transistor to the data driver

Abstract

A LED pixel structure that reduces current nonuniformities and threshold voltage variations in a “drive transistor”of the pixel structure is disclosed. The LED pixel structure incorporates a current source for loading data into the pixel via a data line. Alternatively, an auto zero voltage is determined for the drive transistor prior to the loading of data.

Claims

1. A display comprising a plurality of pixels, each pixel comprising:

a first transistor having a gate, a source and a drain, where said gate is coupled to a select line, where said source is coupled to a data line;

a second transistor having a gate, a source and a drain, where said gate of said second transistor is coupled said select line, where said drain of said second transistor is coupled to a V_DD line, where said source of said second transistor is coupled to said drain of said first transistor;

a third transistor having a gate, a source and a drain, where said gate of said third transistor is coupled said select line;

a capacitor having a first terminal and a second terminal, where said source of said third transistor is coupled to said first terminal of said capacitor, where said second terminal of said capacitor is coupled to said drain of said first transistor;

a fourth transistor having a gate, a source and a drain, where said source of said fourth transistor is coupled to said drain of said first transistor, where said gate of said fourth transistor is coupled said source of said third transistor; and

a light element having two terminals, where said drain of said fourth transistor and said drain of said third transistor are coupled to one of said terminal of said light element.

2. The display of claim 1, wherein said light element is an organic light emitting diode (OLED).

3. The display of claim 1, wherein said first, third and fourth transistors are PMOS transistors and wherein said second transistor is a NMOS transistor.

4. The display of claim 1, further comprising:

a current source coupled to said data line.

5. A display comprising a plurality of pixels, each pixel comprising:

a first transistor having a gate, a source and a drain, where said gate is coupled to a select line, where said source is coupled to a data line;

a second transistor having a gate, a source and a drain, where said gate of said second transistor is coupled a control line, where said source of said second transistor is coupled to a V_DD line, where said drain of said second transistor is coupled to said drain of said first transistor;

a third transistor having a gate, a source and a drain, where said gate of said third transistor is coupled said select line;

a capacitor having a first terminal and a second terminal, where said source of said third transistor is coupled to said first terminal of said capacitor, where said second terminal of said capacitor is coupled to said drain of said first transistor;

a fourth transistor having a gate, a source and a drain, where said source of said fourth transistor is coupled to said drain of said first transistor, where said gate of said fourth transistor is coupled said source of said third transistor; and

a light element having two terminals, where said drain of said fourth transistor and said drain of said third transistor are coupled to one of said terminal of said light element.

6. The display of claim 5, wherein said light element is an organic light emitting diode (OLED).

7. The display of claim 5, wherein said first, second, third and fourth transistors are PMOS transistors.

8. The display of claim 5, further comprising:

a current source coupled to said data line.

9. A display comprising a plurality of pixels, each pixel comprising:

a first transistor having a gate, a source and a drain, where said gate is coupled to a select line, where said source is coupled to a data line;

a first capacitor having a first terminal and a second terminal, where said drain of said first transistor is coupled to said first terminal of said first capacitor;

a second transistor having a gate, a source and a drain, where said source of said second transistor is coupled to a V_DD line, where said gate of said second transistor is coupled to said second terminal of said first capacitor;

a second capacitor having a first terminal and a second terminal, where said gate of said second transistor is coupled to said first terminal of said second capacitor, where said source of said second transistor is coupled to said second terminal of said second capacitor;

a third transistor having a gate, a source and a drain, where said gate of said third transistor is coupled an auto-zero line, where said source of said third transistor is coupled to said gate of said second transistor, where said drain of said third transistor is coupled to said drain of said second transistor;

a fourth transistor having a gate, a source and a drain, where said gate of said fourth transistor is coupled to an illuminate line, where said source of said fourth transistor is coupled to said drain of said third transistor; and

a light element having two terminals, where said drain of said fourth transistor is coupled to one of said terminal of said light element.

10. The display of claim 9, wherein said light element is an organic light emitting diode (OLED).

11. The display of claim 9, wherein said first, second, third and fourth transistors are PMOS transistors.

12. A display comprising a plurality of pixels, each pixel comprising:

a first transistor having a gate, a source and a drain, where said gate is coupled to a select line, where said source is coupled to a data line;

a first capacitor having a first terminal and a second terminal, where said drain of said first transistor is coupled to said first terminal of said first capacitor;

a second transistor having a gate, a source and a drain, where said source of said second transistor is coupled to a VSWP line, where said gate of said second transistor is coupled to said second terminal of said first capacitor;

a second capacitor having a first terminal and a second terminal, where said gate of said second transistor is coupled to said first terminal of said second capacitor, where said source of said second transistor is coupled to said second terminal of said second capacitor;

a third transistor having a gate, a source and a drain, where said gate of said third transistor is coupled an auto-zero line, where said source of said third transistor is coupled to said gate of said second transistor, where said drain of said third transistor is coupled to said drain of said second transistor; and

a light element having two terminals, where said drain of said second transistor is coupled to one of said terminal of said light element.

13. The display of claim 12, wherein said light element is an organic light emitting diode (OLED).

14. The display of claim 12, wherein said first, second, and third transistors are PMOS transistors.

15. A circuit for driving a light element having two terminals, said circuit comprising:

a first transistor having a gate, a source and a drain, where said gate is coupled to a select line, where said source is coupled to a data line;

a first capacitor having a first terminal and a second terminal, where said drain of said first transistor is coupled to said first terminal of said first capacitor;

a second transistor having a gate, a source and a drain, where said source of said second transistor is coupled to a V_DD line, where said gate of said second transistor is coupled to said second terminal of said first capacitor;

a second capacitor having a first terminal and a second terminal, where said gate of said second transistor is coupled to said first terminal of said second capacitor, where said source of said second transistor is coupled to said second terminal of said second capacitor;

a third transistor having a gate, a source and a drain, where said gate of said third transistor is coupled an auto-zero line, where said source of said third transistor is coupled to said gate of said second transistor, where said drain of said third transistor is coupled to said drain of said second transistor; and

a fourth transistor having a gate, a source and a drain, where said gate of said fourth transistor is coupled to an illuminate line, where said source of said fourth transistor is coupled to said drain of said third transistor, where said drain of said fourth transistor is for coupling to the light element.

16. A system comprising:

a display controller; and

a display, coupled to said display controller, where said display comprises a plurality of pixels, where each pixel comprises;

a first transistor having a gate, a source and a drain, where said gate is coupled to a select line, where said source is coupled to a data line;

a first capacitor having a first terminal and a second terminal, where said drain of said first transistor is coupled to said first terminal of said first capacitor;

a second transistor having a gate, a source and a drain, where said source of said second transistor is coupled to a V_DD line, where said gate of said second transistor is coupled to said second terminal of said first capacitor;

a second capacitor having a first terminal and a second terminal, where said gate of said second transistor is coupled to said first terminal of said second capacitor, where said source of said second transistor is coupled to said second terminal of said second capacitor;

a third transistor having a gate, a source and a drain, where said gate of said third transistor is coupled an auto-zero line, where said source of said third transistor is coupled to said gate of said second transistor, where said drain of said third transistor is coupled to said drain of said second transistor;

a fourth transistor having a gate, a source and a drain, where said gate of said fourth transistor is coupled to an illuminate line, where said source of said fourth transistor is coupled to said drain of said third transistor; and

a light element having two terminals, where said drain of said fourth transistor is coupled to one of said terminal of said light element.