Multiple inverter system

• US 6,229,722 B1
• Filed: 12/08/1999
• Issued: 05/08/2001
• Est. Priority Date: 10/09/1997
• Status: Expired due to Term

• Current Assignee: Toshiba Mitsubishi-Electric Industrial Systems Corporation (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hirata, Akio, Satoh, Kazuhiro, Kawakami, Kazuto, Ichikawa, Kosaku
• Primary Examiner(s): NGUYEN, MATTHEW VAN
• Application Number:
  US09/456,317
• Time in Patent Office: 517 Days
• Field of Search: 363/65, 363/71, 363/98, 363/132, 318/801, 318/803, 318/811
• US Class Current: 363/71
• CPC Class Codes: H02M 1/325 with means for allowing continuous operation despite a fault, i.e. fault tolerant converters
• CPC Class Codes: H02M 7/10 arranged for operation in series, e.g. for multiplication of voltage
• CPC Class Codes: H02M 7/49 Combination of the output voltage waveforms of a plurality of converters
• CPC Class Codes: H02M 7/5395 by pulse-width modulation

Abstract

A multiple inverter system of the present invention is disclosed. It includes a plurality of input transformers having secondary windings and a plurality of unit inverter cells connected in series at n stages to compose respective phases and supply the electric power to a multiple phase load in combination with the input transformers. The input transformers have 3n sets of three-phase windings at the secondary side and the secondary windings of the transformers, which are out-of-phase at each phase, are connected to unit inverter cells of each phase at the n-th stages. Further, the present invention is provided with a bypass switch control to melt a fuse that is applicable to a unit inverter given with a circuit closing command by giving this circuit closing command to a bypass switch corresponding to applicable unit inverters in response to an operation abnormality detector and a DC abnormality detector.

Claims

1. A multiple inverter system, comprising:

at least one input transformer having secondary windings; and

a plurality of unit inverter cells connected in series for n-stages (where n is an integer and n≧

3) to compose multiple phases, supplies electric power to a multiple phase load in combination with said input transformers,

said at least one input transformer being provided with 3n sets of three-phase windings at the secondary side and the secondary windings of said transformers are in phase as connected to the inverter cells at each phase output line.

4. A multiple inverter system according to claim 1, wherein:

n-units of said input transformers are provided to n-units of serially connected unit inverter cells for multiple phases, said input transformer having three sets of three phase windings which are π

/3n out of phase at secondary windings sides respectively, and

said secondary windings which are out of phase at each phase are connected to said unit inverter cells at the n-th stage of each phase.

6. A multiple inverter system according to claim 1 or 2 or 3, wherein:

the number of said input transformers are m units (where m is an integer and m≧

1), each of which has 3n sets of three-phase windings at the secondary side and said unit inverter cells at the n-th stage of each phase are connected with said secondary windings which are out of phase at each phase.

7. A multiple inverter system according to claim 1 or 2 or 3, wherein:

the number of said input transformers are m units, each of which has the same secondary windings and each phase is composed of n-sets of unit inverter cells.

8. A multiple inverter system according to claim 1 or 2 or 3, wherein:

said secondary winding of the same phase input transformer is connected to said unit inverter cell at the n-th stage of each phase.

9. A multiple inverter system according to claim 1 or 2 or 3, wherein:

the number of said input transformers are m units, said winding phases at the primary side of said input transformers are shifted so that the primary side is made in the 6m phase structure, and the secondary side has 3n sets of three-phase windings and said unit inverter cell at the n-th stage of each phase is connected with the out of phase secondary winding.

10. A multiple inverter system according to claim 1 or 2 or 3, wherein:

the number of input transformers are m units, said winding phases are shifted so that the primary side of said input transformers is made in the 6m structure, said secondary side of said input transformers has 3n sets of three-phase windings, said unit inverter cell at the n-th stage of each phase is connected with said secondary winding in the same phase at each phase.

11. A multiple inverter system according to claim 1 or 2 or 3, wherein:

the number of said input transformers are m units, each secondary windings of said input transformers is given with a specified reactance so that the input current does not flow intermittently in the state where the specified load current is flowing to said unit inverters.

12. A multiple inverter system according to claim 1 or 2 or 3, further comprising:

a switch capable of cutting off the circuit, being provided with at least one of three-phase winding at said primary side or said secondary side of said input transformer.

13. A multiple inverter system according to claim 1 or 2 or 3, wherein:

a neutral point clamped 3 level inverter is composed of said unit inverter cells.

14. A multiple inverter system according to claim 1 or 2 or 3, wherein:

at least one inverter circuit of a plurality of said unit inverter cells has a function to be able to operate in either the PWM control or the pulse amplitude modulation (PAM) control and other remaining unit inverters have either the PAM control function or the PWM control function only.

15. A multiple inverter system according to claim 1 or 2 or 3, wherein:

a self-turn-off semiconductor device is used as a switch to bypass the output of said unit inverter cell, said switch being connected in antiparallel between the outputs of unit inverter cells.

16. A multiple inverter system according to claim 1 or 2 or 3, wherein:

control means for controlling that at least one stage unit inverter cell does not output voltages, if the output voltage to be supplied to said load is low.

17. A multiple inverter system according to claim 15, wherein:

control means for controlling that said bypass switch of the output portion of at least said one stage unit inverter cell is operated, if said output voltage to be supplied to said load is low.

18. A multiple inverter system according to claim 15, wherein:

control means for controlling that the bypass switch of said inverter cell output portion is operated and bypass switches of other phase unit inverter cells at the same stage are also operated, if some unit inverter cell becomes defective.

19. A multiple inverter system according to claim 15, wherein:

control means for controlling that the bypass switch of said inverter cell output portion is operated and the output voltage of other phase unit inverter cell at the same state as the defective inverter cell is controlled to zero, if some unit inverter cell becomes defective.

20. A multiple inverter system according to claim 15, wherein:

control means for controlling that unit inverter cells other than the unit inverter which operates said bypass switch or controls the output voltage to zero change the PWM operating frequency of said inverter circuit to the frequency at the normal time.

21. A multiple inverter system according to claim 15, wherein:

it is in a structure that the output voltage supplied to said multiple phase load may be changed over by said switch.

22. A multiple inverter system according to claim 1 or 2 or 3, wherein:

said system is in such a structure that the output voltage may be switched due to the 6 kV system and 3 kV system, and 4.2 kV system and 2.4 kV system.

23. A multiple inverter system according to claim 1 or 2 or 3, wherein:

said system is in such a structure that the output may be taken out of each phase position at any stage of the n stages of said unit inverter cells so that the output voltage can be changed over.

24. A multiple inverter system according to claim 1 or 2 or 3, wherein:

a power regenerating function is provided for each phase at least at one stage of said unit inverters of the n stages.

25. A multiple inverter system according to claim 1 or 2 or 3, wherein:

control means for controlling that a circuit of a power regenerating function is PWM controlled so as to return a regenerated power to a power source when there is said power regeneration from said load side.

26. A multiple inverter system according to claim 1 or 2 or 3, wherein:

any unit inverter cell has a function to control a current value through PWM control and when said multiple inverter system is started, by operating said function, the current is forced to flow to said unit inverter cells of all phases and after charging them up to a preset DC voltage value, the AC power source is turned ON.

27. A multiple inverter system according to claim 1, wherein:

if there are provided m units of said input transformers, 3 n unit inverters are divided into 3 n/m units and said divided unit is combined with one input transformer as one set, and m sets are arranged.

28. A multiple inverter system according to claim 1, wherein:

if there are provided the even number of said input transformers, two units are combined back to back and arranged on one straight line.

29. A multiple inverter system according to claim 1, wherein:

if there are provided the even number of said input transformers, two units are arranged facing to each other.

30. A multiple inverter system according to claim 1, wherein:

3 n sets of three-phase secondary windings are connected so as to make percentage impedances uniform when composing secondary windings of said input transformers and out of-phase secondary windings are connected to said unit inverter cells of all phases.

31. A multiple inverter system according to claim 1, wherein:

percentage impedances of 3 n sets of three-phase secondary windings are made uniform when comprising secondary windings of said input transformers and therefore, said three-phase connection is made by respective phase windings that are wound at different locations of a three-phase core, and out-of-phase secondary windings are connected to said unit inverter cells of all phases.

35. A multiple inverter system according to claim 31, wherein:

said abnormal operation detecting means is to detect said output AC voltage of said unit inverter and to detect an abnormality of said unit inverter when said detected voltage is above the specified range against a reference value.

2. A multiple inverter system comprising:

at least one input transformer having a plurality of three-phase secondary windings;

at least one three-phase inverter; and

a plurality of single-phase inverter cells,

said single-phase inverter cells being connected in series for a plurality of stages (n−

1) to compose multiple phases and connected to each of the same phases of said three-phase inverters to supply electric power to a multiple phase load.

5. A multiple inverter system according to claim 2, wherein:

said three-phase inverters and single-phase inverter cells at the (n−

1)th stage which are serially connected for each phase are connected with the secondary windings of the π

/3n out of phase transformers.

3. A multiple inverter system, comprising:

a plurality of input transformers having secondary windings; and

a plurality of unit inverter cells connected in series for n-stages (where n≧

3) to compose multiple phases, supplies electric power to a multiple phase load in combination with said input transformers, said plurality of unit inverter cells being connected to said secondary windings,

wherein said input transformers are provided with 3n sets of three-phase windings at the secondary side, and

wherein secondary windings of said transformers are connected to a stage of said plurality of unit inverter cells in which each secondary winding of a stage is out of phase with the other secondary windings of said stage.

32. A multiple inverter system, comprising;

a rectifier to convert AC power into DC power;

a group of inverters, which are to convert DC power of said rectifier into AC power, provided with a plurality of voltage source unit inverters composing a plurality of bridge connected semiconductor devices, the input sides of said unit inverters connected to said rectifier in parallel via smoothing capacitors, respectively, output sides of said unit inverters connected in series and also connected to an AC load;

a fuse serially connected between said rectifier and said unit inverter;

a bypass switch provided between said rectifier and unit inverter and connected in parallel with said unit inverter and forms a circuit to circulate load current when said circuit is electrically closed;

a unit inverter control means for giving a firing command to semiconductor devices composing said unit inverter in the specified order;

an abnormal operation detecting means for detecting said abnormal operating state of said unit inverter based on said AC output of said unit inverters;

a DC abnormality detecting means for detecting an abnormality of DC input of said unit inverter; and

a bypass switch control means for melting said fuse on applicable to said unit inverter by giving a circuit closing command to said bypass switch corresponding to an applicable unit inverter when both of said abnormal operation detecting means and abnormal DC detecting means detect said abnormality.

33. A multiple inverter system according to claim 32, wherein:

said DC abnormality detecting means is to detect DC abnormality accompanied with said melting of said fuse.

34. A multiple inverter system according to claim 32, wherein:

said DC abnormality detecting means is to detect that the DC voltage applied to said unit inverter is an overvoltage or undervoltage.

36. A multiple inverter system comprising:

a rectifier to convert AC power to DC power;

a group of inverters, which are to convert DC power of said rectifier into AC power, provided with a plurality of voltage source unit inverters composing a plurality of bridge connected semiconductor devices, the input sides of which are connected in parallel with said rectifier via a smoothing capacitor and the output sides of which are connected in series and connected to an AC load;

fuses serially connected between said rectifiers and unit inverters;

bypass switches provided between said rectifiers and said unit inverters, connected in parallel with said unit inverters and form a circuit to circulate load current when said circuit is electrically closed;

a pulse width modulation unit inverter control means for giving a firing command in the specified order to semiconductor devices composing said unit inverters;

an abnormality judging means for making the judgment of troubles related to said unit inverter control means; and

a bypass switch control means for melting said fuse by giving a circuit closing command to said bypass switch of applicable unit inverter when said abnormality judging means judges said abnormality.

37. A multiple inverter system according to claim 36, wherein:

said abnormality judging means makes the judgment based on either the relation of said output voltage of said unit inverter with that of said unit inverter control means, output voltage waveform of said unit inverter control means or the power source abnormality of said unit inverter control means.

38. A multiple inverter system, comprising:

a rectifier to convert AC power to DC power;

a group of inverters, which are to convert DC power of said rectifier into AC power, provided with a plurality of voltage inverters composing a plurality of bridge connected semiconductor devices, the input sides of which are connected in parallel with said rectifier via a smoothing capacitor, the output sides of which are serially connected and to an AC load;

a fuse serially connected between said rectifier and said unit inverter;

bypass switches provided between said rectifiers and said unit inverters, connected in parallel with said unit inverters and form, a circuit to circulate load current when said circuit is electrically closed;

a pulse width modulation unit inverter control means for giving a firing command in the specified order to semiconductor devices comprising said unit inverters;

an operation abnormality detecting means for detecting an abnormal operating state of said unit inverters based on said AC output of said unit inverters;

a DC abnormality detecting means for detecting abnormality of DC input of said unit inverters; and

a bypass switch control means for melting said fuse by giving a circuit closing command to said bypass switch of applicable unit inverter when both of said operation abnormality detecting means and DC abnormality detecting means detect abnormality;

said system is operated by increasing the percentage modulation of said unit inverter in the phase caused abnormality out of said inverter group to more than one time by said unit inverter control means.

39. A multiple inverter system, comprising:

a rectifier to convert AC power into DC power;

a group of inverters, which are to convert DC power of said rectifier into AC power, provided with a plurality of voltage unit inverters composing a plurality of bridge connected semiconductor devices, the input sides of said unit inverters are connected to said rectifier in parallel with it via smoothing capacitors, and the output sides of which are serially connected and to an AC load;

a fuse serially connected between said rectifier and said unit inverter;

bypass switches provided between said rectifiers and said unit inverters, connected in parallel with said unit inverters and form a circuit to circulate load current when said circuit is electrically closed;

a pulse width modulation unit inverter control means for giving a firing command in the specified order to semiconductor devices composing said unit inverters;

an operation abnormality detecting means for detecting an abnormal operating state of said unit inverters based on said AC output of said unit inverters;

a DC abnormality detecting means for detecting abnormality of DC input of said unit inverters; and

a bypass switch control means for melting said fuse by giving a circuit closing command to said bypass switch of applicable unit inverter when both of said operation abnormality detecting means and DC abnormality detecting means detect abnormality;

a group of healthy phase inverters are operated by adapting to the number of inverters in the phase detected by said operation abnormality detecting means.