Reducing waiting time jitter

• US 6,229,863 B1
• Filed: 11/02/1998
• Issued: 05/08/2001
• Est. Priority Date: 11/02/1998
• Status: Expired due to Term

• Current Assignee: CommScope Technologies, LLC (CommScope Holding Company, Inc.)
• Original Assignee: ADC Telecommunications Incorporated (TE Connectivity Limited)
• Inventors: Rude, Michael J.
• Primary Examiner(s): Pham, Chi
• Assistant Examiner(s): CORRIELUS, JEAN B
• Application Number:
  US09/184,627
• Time in Patent Office: 918 Days
• Field of Search: 370/505, 370/506, 370/516, 375/372, 375/371, 375/354
• US Class Current: 375/372
• CPC Class Codes: H04J 3/073 Bit stuffing, e.g. PDH

Abstract

Circuits and methods are described which reduce waiting time jitter at a synchronizer/multiplexer by using a “sub-bit” comparison of a clock associated with an unsynchronized data stream and a clock associated with a synchronized data stream to generate a threshold level for use in determining when to stuff bits into the synchronized data stream. The term “sub-bit” means that the phase difference, as measured by, for example, the location of pointers associated with the two clocks, is precise to a fraction of a bit.

Claims

1. A method for reducing waiting time jitter in a system using bit stuffing synchronization, the method comprising:

receiving an unsynchronized data stream;

writing the data of the unsynchronized data stream to an elastic store;

reading the data from the elastic store as part of a synchronized data stream;

detecting a sub-bit phase difference of clocks associated with the synchronized and unsynchronized data streams;

filtering the sub-bit phase difference;

varying a threshold level based on the filtered sub-bit phase difference;

comparing the clocks associated with the synchronized and unsynchronized data streams with the threshold level; and

controlling the length of frames in the synchronized data stream based on the comparison with the threshold level by selectively stuffing bits into the frames so as to reduce the waiting time jitter.

2. The method of claim 1, wherein detecting a sub-bit phase difference comprises comparing a divided down write clock with a frame synchronization signal for the synchronized data stream using a lead-lag counter.

3. The method of claim 1, wherein detecting a sub-bit phase difference comprises comparing pointers of read and write clocks with a sub-bit precision.

4. The method of claim 1, wherein filtering the sub-bit difference comprises low-pass filtering the sub-bit difference.

5. The method of claim 1, wherein varying the threshold level comprises:

when the sub-bit phase difference is greater than a selected level, setting the threshold at a first level; and

when the sub-bit phase difference is less than the selected level, setting the threshold at a second different level.

6. The method of claim 1, wherein varying the threshold level comprises:

when the sub-bit phase difference is greater than a first selected level, setting the threshold at a first level;

when the sub-bit phase difference is less than a second selected level, setting the threshold at a second different level; and

when the sub-bit phase difference is between the first and second selected levels, setting the threshold at a third level.

7. A method for reducing waiting time jitter in a synchronizer, the method comprising:

generating a sub-bit phase comparison of read and write clocks used to pass unsynchronized data through an elastic store;

comparing read and write pointers for the read and write clocks with a threshold level;

generating a frame of synchronized data from the data in the elastic store with a length that is dependent on the result of comparing the read and write pointers with the threshold level; and

selecting the threshold level used in comparing the read and write pointers based on the generated sub-bit phase comparison so as to reduce waiting time jitter;

wherein generating the sub-bit phase comparison comprises dividing down the write clock and comparing the divided write clock with a frame synchronization signal for the synchronized data.

8. The method of claim 7, wherein selecting the threshold level comprises filtering the sub-bit phase comparison.

9. The method of claim 7, wherein selecting the threshold level comprises:

filtering the sub-bit phase comparison with a low pass filter; and

selecting between at least two threshold levels.

10. The method of claim 9, wherein selecting between at least two threshold levels comprises selecting between −

K, 0 and K unit intervals, wherein a magnitude of the value K is a constant.

11. A synchronizer circuit, comprising:

an elastic store that receives an unsynchronized data stream;

a write clock that controls the writing of data to the elastic store;

a read clock that controls the reading of data from the elastic store;

a multiplexer that receives the data read from the elastic store;

a phase detector that compares the phase of the read and write clocks;

a threshold generator that generates a variable threshold value based on a first output of the phase detector;

a comparator that compares a second output of the phase detector with the threshold value, wherein the second output is different from the first output; and

a control logic coupled to the multiplexer that controls the insertion of stuff bits based on the output of the comparator so as to reduce waiting time jitter.

12. The synchronizer of claim 11, wherein the phase detector produces a sub-bit phase comparison of the read and write clocks.

13. The synchronizer of claim 11, wherein the threshold generator generates the threshold value based on a sub-bit phase comparison from the phase detector.

14. The synchronizer of claim 11, wherein the phase detector includes a lead-lag counter.

15. The synchronizer of claim 11, wherein the threshold generator includes a low pass circuit that filters the first output of the phase detector.

16. The synchronizer of claim 15, wherein the threshold generator includes a limiter circuit that selects a threshold value based on the filtered first output of the phase detector.

17. The synchronizer of claim 11, wherein the first output of the phase detector is a sub-bit component of an output signal of the phase detector, and wherein the second output of the phase detector is a bit-level component of the output signal of the phase detector.

18. The synchronizer of claim 11, wherein the phase detector includes a lead-lag counter controlled by an external clock with a frequency sufficient to create the first output with sub-bit precision, and a phase comparator to produce the second output.

19. A synchronizer, comprising:

an elastic store that receives an unsynchronized data stream;

a multiplexer, coupled to the elastic store, that produces a synchronized data stream from the unsynchronized data stream by the controlled insertion of stuff bits; and

a control circuit that controls the insertion of stuff bits into the synchronized data stream based on a comparison of the phase difference of clocks associated with the synchronized and unsynchronized data streams with a variable threshold level that is generated from a sub-bit phase comparison of clocks associated with the synchronized and unsynchronized data streams so as to reduce waiting time jitter.

20. The synchronizer of claim 19, further comprising:

a low pass filter that receives the sub-bit phase comparison; and

a limiter, coupled to the control circuit, that selects one of at least two threshold levels based on an output of the low pass filter.

21. The synchronizer of claim 19, further comprising a lead-lag counter that generates the sub-bit phase comparison.

22. A telecommunications network, comprising:

a synchronizer;

a desynchronizer;

a synchronous link coupling the synchronizer to the desynchronizer; and

wherein the synchronizer includes;

an elastic store that receives an unsynchronized data stream;

a multiplexer, coupled to the elastic store, that produces a synchronized data stream from the unsynchronized data stream by the controlled insertion of stuff bits; and

a control circuit that controls the insertion of stuff bits into the synchronized data stream based on a comparison of the phase difference of clocks associated with the synchronized and unsynchronized data streams with a variable threshold level that is generated from a sub-bit phase comparison of clocks associated with the synchronized and unsynchronized data streams so as to reduce waiting time jitter.

23. The network of claim 22, further comprising:

a low pass filter that receives the sub-bit phase comparison; and

a limiter, coupled to the control circuit, that selects one of at least two threshold levels based on an output of the low pass filter.

24. The network of claim 22, further comprising a lead-lag counter that generates the sub-bit phase comparison.