Hardware and software co-simulation including executing an analyzed user program
First Claim
1. A co-simulation design system for testing by simulation an electronic system on a host computer system, the electronic system including target digital circuitry, a target processor having a pipeline, and an accompanying user program to be executed on the target processor, the design system comprising:
- a processor simulator using software executing on the host computer system for simulating execution of the user program on the target processor, the software including an analyzed version of the user program;
a hardware simulator to simulate the target digital circuitry using software executing on the host computer system; and
an interface mechanism that couples the hardware simulator with the processor simulator including controlling communication between the processor simulator and the hardware simulator, wherein the processor simulator includes a mechanism to communicate with the hardware simulator using the interface mechanism when an event requires interaction of the user program with the target digital circuitry,wherein the analyzed version of the user program is obtained by decomposing the user program into linear blocks and calculating the time delay that would be incurred by executing each linear block on the target processor, the time calculating incorporating target processor instruction timing and pipeline effects, such that executing the analyzed version of the user program produces timing information incorporating target processor instruction timing and pipeline effects.
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Abstract
A co-simulation design system that runs on a host computer system is described that includes a hardware simulator and a processor simulator coupled via a interface mechanism. The execution of a user program is simulated by executing an analyzed version of the user program on the host computer system. The analysis adds timing information to the user program so that the processor simulator provides accurate timing information whenever the processor simulator interacts with the hardware simulator.
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Citations
71 Claims
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1. A co-simulation design system for testing by simulation an electronic system on a host computer system, the electronic system including target digital circuitry, a target processor having a pipeline, and an accompanying user program to be executed on the target processor, the design system comprising:
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a processor simulator using software executing on the host computer system for simulating execution of the user program on the target processor, the software including an analyzed version of the user program;
a hardware simulator to simulate the target digital circuitry using software executing on the host computer system; and
an interface mechanism that couples the hardware simulator with the processor simulator including controlling communication between the processor simulator and the hardware simulator, wherein the processor simulator includes a mechanism to communicate with the hardware simulator using the interface mechanism when an event requires interaction of the user program with the target digital circuitry, wherein the analyzed version of the user program is obtained by decomposing the user program into linear blocks and calculating the time delay that would be incurred by executing each linear block on the target processor, the time calculating incorporating target processor instruction timing and pipeline effects, such that executing the analyzed version of the user program produces timing information incorporating target processor instruction timing and pipeline effects. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
wherein the processor simulator and the hardware simulator process independently of each other. -
3. The design system of claim 1,
wherein the processor simulator communication mechanism communicates information associated with the event to the hardware simulator, and wherein the hardware simulator receives the associated event information. -
4. The design system of claim 3,
wherein the hardware simulator processes the associated event information. -
5. The design system of claim 4,
wherein the event information includes time delay information indicating an amount of simulated time since a previous event, and wherein, upon receiving the time delay information, the hardware simulator executes an appropriate amount of hardware simulation time. -
6. The design system of claim 5, wherein the time delay information is forwarded to the hardware simulator when no event information has been conveyed to the hardware simulator within a predetermined amount of time.
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7. The design system of claim 4, further comprising
a suspend mechanism coupled to the processor simulator that temporarily halts execution of the user program on the processor simulator while the hardware simulator processes the event information. -
8. The design system of claim 7, wherein the interface mechanism includes the suspend mechanism.
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9. The design system of claim 4,
wherein the hardware simulator processing the event information produces an event result, and, wherein the hardware simulator includes a mechanism to communicate the event result to the processor simulator using the interface mechanism. -
10. The design system of claim 9, wherein the event result is an interrupt, and is processed upon receipt of the event result by the processor simulator.
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11. The design system of claim 9, further including
a resumption mechanism coupled to the processor simulator to resume execution of the user program upon receipt of the event result. -
12. The design system of claim 9,
wherein the hardware simulator contains a processor model shell to access at least some of the external hardware signals of the target processor connected to the digital circuitry in the electronic system, and wherein the processor simulator uses a first data format and the hardware simulator uses a second data format, the design system further including a mapper to map an event result in the second data format to the first data format. -
13. The design system of claim 12, wherein the host computer system includes a computer network, wherein the processor simulator is coupled to the translator and the mapper by a first computer network connection of the computer network, the interface mechanism controlling communication between the processor simulator, and the translator and the mapper over the first network connection.
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14. The design system of claim 13, wherein the translator and the mapper are coupled to the hardware simulator by a second computer network connection of the computer network, the interface mechanism controlling communication between the translator and the mapper, and the hardware simulator over the first and second network connections.
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15. The design system of claim 1,
wherein the host computer system includes a computer network containing a first and a second host computer, wherein the processor simulator operates on the first host computer, wherein the hardware simulator operates on the second host computer, and wherein the processor simulator is coupled to the hardware simulator by a computer network connection of the computer network, and wherein the interface mechanism controls communications over the network connection. -
16. The design system of claim 1, wherein the event requiring the user program to interact with the target digital circuitry is an input/output instruction to the hardware simulator.
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17. The design system of claim 1, wherein the processor simulator uses a first data format and the hardware simulator uses a second data format, the system further including a translator to convert the associated event information from the first data format to the second data format.
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18. The design system of claim 1,
wherein the user program includes statements in a higher-level language, wherein decomposing the user program into linear blocks includes parsing the user program to determine linear block boundaries, wherein calculating the time delay for each linear block comprises: -
cross compiling the user program to produce target code;
parsing the cross compiled target code to determine the time delay for each line in each section of the target code corresponding to each linear block in the user program, the time delay determining using characteristics of the target processor; and
calculating the time delay for each linear block of the user program from the time delays determined in the target code parsing step.
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19. The design system of claim 18, wherein the analyzed user program includes instructions for accumulating the calculated linear block time delays, and executing the analyzed program includes executing the user program and executing the time delay accumulation instructions.
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20. The design system of claim 18, wherein executing the analyzed program includes executing the user program while making reference to the calculated linear block time delays.
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21. The design system of claim 1, wherein the hardware simulator operates in a hardware description languages, and at least some of the digital circuitry is specified in the hardware description language.
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22. The design system of claim 1, wherein the hardware simulator provides for modeling digital circuitry in a higher-level language and, wherein at least some of the digital circuitry is specified in the higher-level language.
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23. The design system of claim 1, wherein the interface mechanism includes a message passing kernel.
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24. The design system of claim 23, wherein the processor simulator and the hardware simulators are tasks under the kernel.
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25. The design system of claim 23, wherein the host computer system includes a plurality of host processors, and, wherein the processor simulator and the hardware simulators execute on different host processors.
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26. A co-simulation design system for testing by simulation an electronic system on a host computer system, the electronic system including target digital circuitry, first and second target processors, and accompanying first and second user programs to be executed on each of the target processors, at least one of the target processors having a pipeline, the design system comprising:
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a first processor simulator using software executing on the host computer system for simulating execution of the first user program on the first target processor, the software including an analyzed version of the first user program;
a second processor simulator using software executing on the host computer system for simulating execution of the second user program on the second target processor, the software including an analyzed version of the second user program;
(b) simulating the target digital circuitry on a hardware simulator operating on the host computer system, the simulating of the target digital circuitry including accumulating timing information;
(c) passing communication between the simulated target processor and the hardware simulator at significant events, including events that require interaction between the user program and the target digital circuitry. - View Dependent Claims (27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42)
wherein the first processor simulator communication mechanism communicates information associated with the first user program event to the hardware simulator, wherein the second processor simulator communication mechanism communicates information associated with the second user program event to the hardware simulator, wherein the hardware simulator receives the first user program associated event information, and wherein the hardware simulator receives the second user program associated event information. -
29. The design system of claim 28,
wherein the hardware simulator processes the first user information associated event information, generating a first user program event result, and wherein the hardware simulator processes the second user information associated event information, generating a second user program event result. -
30. The design system of claim 29,
wherein each event information includes time delay information indicating an amount of simulated time since the hardware simulator last received previous event information from the respective user program, and wherein, upon receiving the time delay information from either of the processor simulators, the hardware simulator executes an appropriate amount of hardware simulation time. -
31. The design system of claim 30, wherein the time delay information is forwarded to the hardware simulator from either of the processor simulator when no event information has been conveyed by that processor simulator to the hardware simulator within a predetermined amount of time.
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32. The design system of claim 29, wherein the hardware simulator processes the event information producing an event result for information associated with each event, and
wherein the hardware simulator includes a mechanism to communicate the event result to the respective processor simulator whose user program produced the event, using the interface mechanism. -
33. The design system of claim 32, wherein one of the event results is an interrupt for a particular target processor, and is processed upon receipt of the event result by one of the processor simulator associated to the event.
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34. The design system of claim 32 further including first and second resumption mechanisms respectively coupled to the first and second processor simulators to resume execution of the respective user program upon receipt of the respective user program event result.
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35. The design system of claim 26,
wherein the host computer system includes a computer network containing a first and a second host computer, wherein the processor simulator operates on the first host computer, wherein the hardware simulator operates on the second host computer, wherein the processor simulator is coupled to the hardware simulator by a computer network connection of the computer network, and wherein the interface mechanism controls communications over the network connection. -
36. The design system of claim 26, further comprising:
first and second suspend mechanisms respectively coupled to the first and second processor simulators, each suspend mechanism temporarily halting execution of the respective user program on the respective processor simulator while the hardware simulator processes the respective user program event information.
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37. The design system of claim 36,
wherein the interface mechanism includes the suspend mechanisms. -
38. The design system of claim 26,
wherein the host computer system includes a computer network, and, wherein the first and second processor simulators are each coupled to the hardware simulator by a respective computer network connection of the computer network, the interface mechanism controlling communications over the network connections. -
39. The design system of claim 26,
wherein the one of the user program events is an input/output instruction to the hardware simulator, and wherein the interface mechanism controls communication of the input/output instruction from the event-associated processor simulator to the hardware simulator. -
40. The design system of claim 26,
wherein the first and second processor simulators use a first data format and the hardware simulator uses a second data format, the system further including a translator to convert the events when the first or second user program for the first or second target processor, respectively, requires interaction with the target digital circuitry from the first data format to the second data format. -
41. The design system of claim 40, wherein the hardware simulator contains first and second processor model shells to simulate activation of the pins of the first and second target processors, respectively, the system further including a mapper to map an event result in the second data format to the first processor data format.
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42. The design system of claim 26, wherein the interface mechanism includes a message passing kernel.
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43. A method of simulating an electronic system that includes target digital circuitry and a target processor having a pipeline, the method comprising:
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(a) simulating executing the user program executing on a target processor by executing an analyzed version of the user program on the host processor, the executing of the analyzed version including accumulating timing information according to the target processor characteristics, the timing information including instruction timing and pipeline effects, information, the block timing information taking into account instruction timing and pipeline effects. - View Dependent Claims (44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58)
(d) modeling one or more aspects of the target processor execution at a user selected level of detail.
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46. The method according to claim 45, wherein the analyzing step further comprises:
inserting code into the user program that causes at run time the one or more aspects of the target processor execution to be simulated at the selected level of accuracy.
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47. The method according to claim 45, wherein the one or more aspects are modeled in hardware, and wherein the inserted code causes the one or more aspects to be simulated on the hardware simulator.
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48. The method according to claim 44, wherein the analyzing step further comprises:
inserting code into the user program for detecting execution exceptions at execution time.
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49. The method according to claim 43, wherein one of the significant events is a particular event requiring the user program to interact with the hardware simulator, and wherein the communication is information associated with the particular event, the associated event passed to the hardware simulator.
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50. The method according to claim 49, further comprising:
(d) receiving and processing the associated event information at the processor simulator.
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51. The method according to claim 50, wherein the associated event information includes time delay information indicating an amount of simulated time since a previous significant event, and wherein said step (d) of processing executes an appropriate amount of hardware simulation time.
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52. The method according to claim 51, further comprising:
(e) suspending step (a) of simulating execution of the user program while the associated event information is processed in said step (d).
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53. The method according to claim 52, wherein said associated event processing step (d) produces an event result, the method further including:
(f) resuming said execution user program simulating step (a) when the event result is produced.
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54. The method according to claim 53, wherein the event result is an asynchronous event, and wherein said resuming step (b) causes simulation of execution of an asynchronous event handler, the handler being part of the user program.
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55. The method according to claim 54, wherein the asynchronous event occurs before the processor simulator executes the appropriate amount of hardware simulation time.
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56. The method according to claim 55, wherein simulating the handler execution accumulates a handler delay time, the method further comprising
examining the user program to ensure that the interrupt handler part of the user program does not share variables with any other part of the user program; -
completing processing of the appropriate amount of time on the hardware simulator, processing a further amount of simulation time corresponding to the handler delay time on the hardware processor.
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57. The method according to claim 54, further including avoiding the asynchronous event occurring before the processor simulator executes the appropriate amount of hardware simulation time.
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58. The method according to claim 51, wherein said associated event processing step (d) produces an event result.
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59. A method for creating a processor model for simulating the operation of a target processor executing a user program, the processor model for use in a simulation design system operable on a host computer system to simulate an electronic system that contains target digital circuitry and the target processor, the target processor having a pipeline, the design system including a hardware simulator for simulating the digital circuitry on the host computer system, the method comprising:
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(a) creating a processor model shell for operation on the hardware simulator, the processor model shell accessing one or more signals of the target processor accessible to digital circuitry external to the target processor;
(b) creating a software shell to provide the user program access to the processor signals coupled to the digital circuitry in the electronic system; and
(c) creating target processor specific information for use in analyzing a user program to determine user program timing information such that when the user program is run on a processor simulator operating on the host computer system, the processor simulator simulates execution, including providing timing, as if the user program was executing on the target processor, the timing taking into account instruction timing and pipeline effects, the user program analyzing including decomposing the user program into linear blocks, determining linear block timing information including the time delays that would be incurred executing each linear block of the user program on the target processor, the block timing information determining using the target processor specific a hardware simulator to simulate the target digital circuitry using software executing on the host computer system; and
an interface mechanism that couples the hardware simulator with the first and second processor simulators, including controlling communication between the first and second processor simulators and the hardware simulator, wherein the first processor simulator includes a first mechanism to communicate with the hardware simulator using the interface mechanism when an event requires interaction of the first user program with the target digital circuitry, wherein the second processor simulator includes a second mechanism to communicate with the hardware simulator using the interface mechanism when an event requires interaction of the second user program with the target digital circuitry, wherein the analyzed versions of the each user program are obtained by decomposing the respective user program into linear blocks and calculating the time delay that would be incurred by executing each linear block on the respective target processor, the time calculating incorporating respective target processor'"'"'s instruction timing and pipeline characteristics, such that executing the analyzed version of the user program produces timing information incorporating the respective target processor instruction timing including any pipeline effects. - View Dependent Claims (60, 61, 62, 63, 64, 65, 66, 67, 68)
wherein the hardware simulator simulates hardware described in a hardware description language, and wherein the processor model shell comprises an interface in the hardware description language. -
61. The method of claim 60, wherein the software shell comprises higher-level computer language code.
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62. The method of claim 59,
wherein the hardware simulator simulates hardware using a higher-level language, and wherein the processor model shell comprises an interface in the higher-level language. -
63. The method of claim 59,
wherein the user program includes higher-level computer language code, wherein determining the time delay for each linear block comprises: -
cross compiling the user program to produce target code;
parsing the cross compiled target code to determine the time delay for each line in each section of the target code corresponding to each linear block in the user program; and
determining the time delay for each linear block of the user program from the time delays determined in the target code parsing step, and wherein the target processor specific information includes information on how to parse cross compiled target code.
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64. The method of claim 59,
wherein the hardware simulator defines the simulation time frame, and wherein the software shell further provides a user program access to the hardware simulator for the purpose of user program time control. -
65. The method of claim 59, further including:
selecting a level of detail of the processor model.
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66. The method of claim 65, wherein said selecting a level of detail further includes:
modeling in hardware one or more aspects of the target processor execution where greater accuracy is desired, execution of the one or more aspects simulated by the hardware simulator.
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67. The method of claim 65, wherein the user program analyzing further includes inserting code into the user program that simulates at execution time one or more aspects of the target processor execution where greater accuracy is desired.
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68. The method of claim 67, wherein inserted code includes code that causes the hardware simulator to simulate at least part of the one or more aspects of the target processor execution.
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69. A method of simulating on a host computer system the execution of a user program on a target processor having a pipeline, the target processor being part of an electronic system that includes target digital circuitry, the method comprising:
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(a) decomposing the user program into linear blocks;
(b) determining linear block timing information including the time delays that would be incurred executing each linear block of the user program on the target processor, the determining using characteristics of the target processor including instruction timing and pipeline characteristics, the block timing information taking into account instruction timing and pipeline effects;
(c) combining the linear block timing information with the user program;
(d) executing the combined user program and linear block timing information on the host computer system; and
(e) simulating the target digital circuitry on a hardware simulator running on the host computer system, wherein execution of the combined user program and linear block timing information on the host computer system includes communicating with the hardware simulator when an event requires interaction of the user program with the target digital circuitry, such that the execution of the combined user program and linear block timing information on the host computer system simulates the execution of the user program on the target processor including providing execution timing that takes into account instruction timing and pipeline effects. - View Dependent Claims (70, 71)
wherein the user program includes statements in a higher-level language, wherein the step of decomposing the user program into linear blocks includes parsing the user program to determine linear block boundaries, wherein determining the time delay for each linear block comprises: cross compiling the user program to produce target code;
parsing the cross compiled target code to determine the time delay for each line in each section of the target code corresponding to each linear block in the user program, the time delay determining using characteristics of the target processor; and
determining the time delay for each linear block of the user program from the time delays determined in the target code parsing step.
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71. The method of claim 70,
wherein combining the linear block timing information with the user program produces an analyzed user program that includes instructions for accumulating the timing delay, and wherein the executing executes the analyzed user program on the host processor.
Specification