Digital signal processor configuration including multiplying units coupled to plural accumlators for enhanced parallel mac processing

• US 6,230,180 B1
• Filed: 10/14/1998
• Issued: 05/08/2001
• Est. Priority Date: 10/14/1998
• Status: Expired due to Term

• Current Assignee: Callahan Cellular LLC (Intellectual Ventures LLC)
• Original Assignee: Conexant Systems Incorporated (Synaptics Incorporated)
• Inventors: Mohamed, Moataz A.
• Primary Examiner(s): Kim, Kenneth S.
• Application Number:
  US09/172,527
• Time in Patent Office: 937 Days
• Field of Search: 708/603, 708/523, 708/524, 712/22, 712/221
• US Class Current: 708/523
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3893 controlled in tandem, e.g. multiplier-accumulator

Abstract

The present invention generally relates to multiply-accumulate units for use in digital signal processors. Each multiply-accumulate unit includes a multiply unit which is coupled with two or more dedicated accumulators. Because of the coupling configuration, when an instruction specifies which accumulator should be used in executing an operation, the instruction need not specify which multiply unit should be utilized. A scheduler containing a digital signal processor'"'"'s coupling configuration may then identify the multiply unit associated with the accumulator and may then forward the instruction to the identified multiply unit. Multiply-accumulate units can be configured to execute both scalar and vector operations. For executing vector operations, multiply units and their coupled accumulators are configured such that each may be easily grouped with other multiply units and accumulators.

Claims

1. A digital signal processor having a plurality of processing elements for use in executing a first instruction and a second instruction, said processor comprising:

a first multiplying element which executes a first instruction and multiplies at least two operands resulting in a product;

a first plurality of accumulating elements, each having an associated value and each being coupled to said first multiplying element;

a second multiplying element;

a second plurality of accumulating elements coupled to said second multiplying element;

a copying element which copies data from said different first accumulating element into one of said second plurality of accumulating elements; and

an alteration element which forwards said second instruction to said second multiplying element for execution, wherein;

said first instruction uses one of said first plurality of accumulating elements and said second instruction uses a different one of said first plurality of accumulating elements.

2. A method of performing a MAC operation in a digital signal processor having a plurality of multiplying elements, each of which is coupled to a plurality of accumulating elements, comprising the steps of:

receiving an instruction in a scheduler, said instruction specifying a first of said plurality of accumulating elements;

identifying a first one of said plurality of multiplying elements that is coupled to said first accumulating element;

transmitting said instruction from said scheduler to said first multiplying element;

retrieving a plurality of operands located in a number of registers for use in said first multiplying element;

multiplying in said first multiplying element said plurality of operands resulting in a product;

adding said product to a stored value in said first accumulating element resulting in a total; and

storing said total in said first accumulating element.

3. The method of claim 2, wherein a second of said plurality of multiplying elements is coupled to a second of said plurality of accumulating elements and wherein said instruction is a vector instruction, said method further comprising:

configuring said first multiplying element with said second multiplying element to operate in combination with one another in response to said instruction; and

configuring said first accumulating element and said second accumulating element to operate in combination with one another in response to said instruction.

4. The method of claim 2, further comprising:

identifying said plurality of multiplying elements and said plurality of accumulating elements by a consecutive indexing scheme; and

configuring said plurality of accumulating elements such that said consecutive accumulating elements are coupled to different elements selectable from said plurality of multiplying elements.

5. A digital signal processor comprising:

a plurality of first functional units which are operatively associated with a plurality of second functional units;

a number of register files having a plurality of data elements;

an instruction specifying one of said plurality of second functional units and at least one of said plurality of data elements; and

a scheduler which receives said instruction and determines which one of said plurality of first functional units is operatively associated with said one second functional unit,

wherein said one first functional unit receives said instruction, performs an operation on said at least one data element, and achieves a result.

6. The processor of claim 5, wherein said plurality of first functional units are multiplying elements and said plurality of second functional units are accumulating elements.

7. The processor of claim 5, wherein a second of said plurality of first functional units is operatively associated with a second of said plurality of second functional units, wherein said one first functional unit and said second first functional unit are configured to operate in combination with one another in response to said instruction, and wherein said one second functional unit and said second second functional unit are configured to operate in combination with one another in response to said instruction.

8. The processor of claim 7, wherein said plurality of first functional units are multiplying elements and said plurality of second functional units are accumulating elements.

9. The processor of claim 7, wherein said plurality of multiplying elements and said plurality of second functional units are identified by a consecutive indexing scheme such that said consecutive indexed second functional units are operatively associated with different units selectable from said plurality of first functional units.

10. The processor of claim 9, wherein said plurality of first function units are multiplying elements and said plurality of second functional units are accumulating elements.