High performance multichannel DMA controller for a PCI host bridge with a built-in cache

• US 6,230,219 B1
• Filed: 11/10/1997
• Issued: 05/08/2001
• Est. Priority Date: 11/10/1997
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Fields, James Stephen Jr., Guthrie, Guy Lynn
• Primary Examiner(s): Beausoleil, Robert
• Assistant Examiner(s): PHAN, RAYMOND NGAN
• Application Number:
  US08/966,873
• Time in Patent Office: 1,275 Days
• Field of Search: 710/126-128, 710/112-113, 710/22, 710/24, 710/27, 710/31, 710/33, 710/38, 710/39, 710/20-21, 710/28-29, 710/129
• US Class Current: 710/22
• CPC Class Codes: G06F 13/30 with priority control

Abstract

A host bridge having a dataflow controller is provided. In a preferred embodiment, the host bridge contains a read command path which has a mechanism for requesting and receiving data from an upstream device. The host bridge also contains a write command path that has means for receiving data from a downstream device and for transmitting the received data to an upstream device. A target controller is used to receive the read and write commands from the downstream device and to steer the read command toward the read command path and the write command toward the write command path. A bus controller is also used to request control of an upstream bus before transmitting the request for data of the read command and transmitting the data of the write command.

Claims

1. A host bridge having a dataflow controller comprising:

a read command path having means for requesting and receiving data from an upstream device;

a write command path having means for receiving data from a downstream device and for transmitting said received data to an upstream device;

a target controller for receiving read and write commands from said downstream device and for steering said read command toward said read command path and said write command toward said write command path; and

a bus controller for requesting control of an upstream bus before transmitting said data request of said read command and transmitting said data of said write command.

2. The host bridge of claim 1 wherein said write data path includes a plurality of channels, each channel having means for storing and transmitting data to said upstream device.

3. The host bridge of claim 2 wherein said means for storing data includes a buffer having a plurality of sections, each section corresponding to a channel.

4. The host bridge of claim 3 wherein each section of said buffer includes a plurality of sectors, each sector being able to pass data to said bus controller.

5. The host bridge of claim 1 wherein said read data path includes a plurality of channels, each channel having means for requesting and storing data from said upstream device.

6. The host bridge of claim 5 wherein said means for storing data includes a buffer having a plurality of sections, each section corresponding to a channel.

7. The host bridge of claim 6 wherein each section of said buffer includes a plurality of sectors, each sector being able to transmit data to said downstream device.

8. The host bridge of claim 7 each sector includes means to request data from said upstream device.

9. The host bridge of claim 8 further comprising a plurality of data catchers, said data catchers temporarily storing data destined to said buffer sectors.

10. The host bridge of claim 9 further comprising an arbiter, said arbiter allowing a downstream device to transmit a request for to said host bridge and disallowing said downstream device to transmit repeats of said data request to said host bridge until the requested data is available in said buffer.

11. A method of flowing data through a host bridge comprising the steps of:

obtaining a read command for requesting and receiving data from an upstream device;

obtaining a write command for receiving data from a downstream device and transmitting said received data to an upstream device;

steering said read command toward a read command path and said write command toward a write command path; and

requesting control of an upstream bus before transmitting said data request of said read command and transmitting said data of said write command.

12. The method of claim 11 further comprising the step of storing and transmitting data to said upstream device in a plurality of channels.

13. The method of claim 12 wherein the step of storing includes storing data into a buffer having a plurality of sections, each section corresponding to a channel.

14. The method of claim 13 wherein each section of said buffer includes a plurality of sectors, each sector being able to pass data to said bus controller.

15. The method of claim 11 wherein said read data path includes a plurality of channels, each channel being able to request and store data from said upstream device.

16. The method of claim 15 wherein storing data includes a buffer having a plurality of sections, each section corresponding to a channel.

17. The method of claim 16 wherein each section of said buffer includes a plurality of sectors, each sector being able to transmit data to said downstream device.

18. The method of claim 17 wherein each sector includes means to request data from said upstream device.

19. The method of claim 18 further comprising the step of temporarily storing data destined to said buffer sectors in a plurality of data catchers.

20. The method of claim 19 further comprising the step of allowing a downstream device to transmit a request for data to said host bridge and disallowing said downstream device to transmit repeats of said data request to said host bridge until the requested data is available in said buffer.

21. A host bridge having a dataflow controller comprising:

a read channel for receiving read data;

a write channel for receiving write data; and

a target controller for receiving read and write commands and for steering said read command toward said read channel and said write command toward said write channel.

22. The host bridge of claim 21 wherein said read channel for receiving read data from an upstream device and said write channel for receiving write data from a downstream device.

23. The host bridge of claim 22 wherein said read channel for receiving read request commands from a downstream device and said write channel for receiving write request commands from a downstream device.

24. The host bridge of claim 23 further comprising a bus controller for requesting control of an upstream bus before transmitting said read and write data and said read and write request commands.