Dual purpose apparatus method and system for accelerated graphics or second memory interface

• US 6,230,223 B1
• Filed: 06/01/1998
• Issued: 05/08/2001
• Est. Priority Date: 06/01/1998
• Status: Expired due to Fees

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Olarig, Sompong P.
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): ELAMIN, ABDELMONIEM I
• Application Number:
  US09/088,131
• Time in Patent Office: 1,072 Days
• Field of Search: 710/126, 710/110, 710/101, 710/113, 710/104, 710/56, 712/32, 712/33, 712/36, 712/38
• US Class Current: 710/312
• CPC Class Codes: G06F 13/14 Handling requests for interconnection or transfer

Abstract

A multiple use core logic chipset is provided in a computer system that may be configured either as a bridge between an accelerated graphics port (“AGP”) bus and host and memory buses, or as a second memory interface. The function of the multiple use chipset is determined at the time of manufacture of the computer system, or in the field whether an AGP bus bridge or a second memory interface is to be implemented. Selection of the type of bus bridge (AGP or second memory interface) in the multiple use core logic chipset may be implemented by a hardware signal input, or by software during computer system configuration or power on self test (“POST”). Software configuration may also be determined upon detection of either an AGP device or a second memory connected to the core logic chipset.

Claims

1. A computer system having a core logic chipset configurable for either an accelerated graphics port (AGP) or a second memory port, said system comprising:

a central processing unit connected to a host bus;

a first random access memory connected to a first random access memory bus;

a core logic chipset connected to the host bus and the first random access memory bus;

said core logic chipset configured as a first interface bridge between the host bus and the first random access memory bus, a second interface bridge between the host bus and a peripheral component interconnect bus, and a third interface bridge between the first random access memory bus and the peripheral component interconnect bus;

said core logic chipset configurable as a fourth interface bridge between the first random access memory bus and an accelerated graphics port (AGP) bus when a configuration signal is at a first logic level;

said core logic chipset configurable as a fifth interface bridge between the host bus and the AGP bus when the configuration signal is at the first logic level; and

said core logic chipset configurable as a sixth interface bridge between the host bus and a second random access memory bus when the configuration signal is at a second logic level.

2. The computer system of claim 1, wherein the central processing unit is a plurality of central processing units.

3. The computer system of claim 1, wherein the core logic chipset is at least one integrated circuit.

4. The computer system of claim 3, wherein the at least one integrated circuit core logic chipset is at least one application specific integrated circuit.

5. The computer system of claim 3, wherein the at least one integrated circuit core logic chipset is at least one programmable logic array integrated circuit.

6. The computer system of claim 1, further comprising at least one peripheral component interconnect device, the at least one peripheral component interconnect device connected to the peripheral component interconnect bus.

7. The computer system of claim 1, further comprising an AGP device connected to the AGP bus.

8. The computer system of claim 7, wherein the configuration signal is software controllable and is set to the first logic level when the AGP device is determined to be connected to the AGP bus.

9. The computer system of claim 1, further comprising a second random access memory connected to the second random access memory bus.

10. The computer system of claim 9, wherein the configuration signal is software controllable and is set to the second logic level when the second random access memory is determined to be connected to the second random access memory bus.

11. The computer system of claim 1, wherein the host bus, AGP bus, PCI bus, first and second random access memory buses, and core logic chipset are on a printed circuit board.

12. The computer system of claim 11, wherein the configuration signal logic level is determined by a hardwired jumper circuit on the printed circuit board.

13. The computer system of claim 1, wherein the configuration signal logic level is determined by software.

14. The computer system of claim 13, wherein the configuration signal logic level is determined during power on self test of the computer system.

15. The computer system of claim 13, wherein the configuration signal logic level is determined during configuration of the computer system.

16. A method, in a computer system, of configuring a core logic chipset for either an accelerated graphics port (AGP) bus or a second memory port, said method comprising the steps of:

providing a central processing unit connected to a host bus;

providing a first random access memory connected to a random access memory bus;

providing a core logic chipset connected to the host bus and the first random access memory bus;

configuring said core logic chipset as a first interface bridge between the host bus and the first random access memory bus, a second interface bridge between the host bus and a first peripheral component interconnect bus, and a third interface bridge between the random access memory bus and the first peripheral component interconnect bus;

configuring said core logic chipset as a fourth interface bridge between the first random access memory bus and an accelerated graphics port (AGP) bus when detecting a configuration signal at a first logic level;

configuring said core logic chipset as a fifth interface bridge between the host bus and the AGP bus when detecting the configuration signal at the first logic level; and

configuring said core logic chipset configurable as a sixth interface bridge between the host bus and a second random access memory bus when detecting the configuration signal at a second logic level.

17. The method of claim 16, further comprising setting the configuration signal logic level with a hardware jumper.

18. The method of claim 16, further comprising setting the configuration signal logic level with software running in the computer system.

19. The method of claim 18, wherein the step of setting the configuration signal to the first logic level is done when an AGP device is detected.

20. The method of claim 18, wherein the step of setting the configuration signal to the second logic level is done when a second random access memory is detected.

21. A core logic chipset configurable for either an accelerated graphics port (AGP) or a second memory port, comprising:

a processor interface adapted for connection to a computer system processor bus having at least one central processing united connected thereto;

a first memory interface adapted for connection to a first random access memory bus;

a second memory interface adapted for connection to a second random access memory bus;

an accelerated graphics port (AGP) interface adapted for connection to an AGP bus;

a peripheral component interconnect (PCI) interface adapted for connection to a PCI bus;

said AGP interface comprises a request queue, a reply queue, data and control logic, an arbiter, and a PCI to PCI bridge;

said AGP request and reply queues are connected to said first memory interface and said processor interface;

said PCI interface is connected to said first memory interface and said processor interface;

said PCI to PCI bridge is connected to said AGP data and control logic, wherein said PCI to PCI bridge transfers PCI information transactions between said PCI bus and said AGP data and control logic;

said AGP interface is functionally enabled when a control signal having a first logic level is detected; and

said second memory interface is functionally enabled when the control signal having a second logic level is detected.

22. The core logic chipset according to claim 21, wherein said control signal logic level is determined by a hardware jumper signal connected to said AGP and second memory interfaces.

23. The core logic chipset according to claim 21, wherein said control signal logic level is determined by software configuring a control register in said core logic chipset.