Method of self programmed built in self test
First Claim
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1. A method of testing a Dynamic Random Access Memory (DRAM), comprising:
- providing a DRAM core;
providing a Built In Self Test (BIST) engine connected to control said DRAM core during a test condition;
providing a command register for providing control commands to said BIST engine;
providing a self-program circuit for selectively providing commands to said command register, and then testing the DRAM core with said commands.
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Abstract
A method of self-programmable Built In Self Test (BIST) for a memory (e.g., Dynamic Random Access Memory (DRAM)). The DRAM, which may be a DRAM chip, includes a DRAM core, a Microcode or Initial Command ROM, a BIST Engine, a Command Register and a Self-Program Circuit. During self test, the BIST engine may test the DRAM normally until an error is encountered. When an error is encountered, the Self-Program Circuit restarts the self test procedure at less stringent conditions. Optionally, when the DRAM tests error-free, the Self-Program Circuit may restart testing at more stringent conditions to determine DRAM functionality limits.
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Citations
20 Claims
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1. A method of testing a Dynamic Random Access Memory (DRAM), comprising:
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providing a DRAM core;
providing a Built In Self Test (BIST) engine connected to control said DRAM core during a test condition;
providing a command register for providing control commands to said BIST engine;
providing a self-program circuit for selectively providing commands to said command register, and then testing the DRAM core with said commands. - View Dependent Claims (2, 3, 4, 5, 6, 7)
an address counter;
a instruction pointer;
a control signal generator for providing control signals to said DRAM and to said address counter;
a clock generator for supplying a clock signal to said control signal generator, said initial command store and said instruction pointer;
a data pattern generator for supplying test patterns to said DRAM core; and
,a data comparator for comparing supplied patterns with data read from said DRAM core and for providing said test indication.
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5. The method of claim 4, wherein the BIST engine further comprises a voltage control for selecting a test voltage of said DRAM core.
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6. A method of testing a chip including said DRAM comprising the method of claim 5.
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7. The method of claim 2, wherein the self-program circuit comprises:
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a RAM, test indications being stored in said RAM; and
a microprocessor unit for interrogating said test indications, determining a next BIST instruction therefrom and providing said next BIST instruction to said command register, said microprocessor unit including a microprogram ROM for providing commands to said microprocessor.
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8. A method of testing a DRAM chip, comprising:
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providing a DRAM core;
providing a Built In Self Test (BIST) engine connected to supply control signals to said DRAM core;
providing an initial command store;
providing a command register for receiving commands from said initial command store and for providing control commands to said BIST engine;
providing a self-program circuit for selectively providing commands to said command register, and then testing the DRAM core with said commands. - View Dependent Claims (9, 10, 11, 12, 13)
an address counter;
a instruction pointer;
a control signal generator for providing control signals to said DRAM and to said address counter;
a clock generator for supplying a clock signal to said control signal generator, said initial command store and said instruction pointer;
a data pattern generator for supplying test patterns to said DRAM core; and
a data comparator for comparing supplied patterns with data read from said DRAM core and for providing said test indication.
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13. The method of claim 12, wherein the self-program circuit comprises:
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a RAM, said test indication being stored in said RAM; and
a microprocessor unit for interrogating said test indications, determining a next BIST instruction therefrom and providing said next BIST instruction to said command register, said microprocessor unit including a microprogram ROM providing commands to said microprocessor.
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14. A method of self testing a DRAM, comprising the steps of:
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loading an initial self test instruction into a control register;
executing said self test instruction;
storing the results of executing said self test instruction;
determining from the stored results whether a DRAM meets test criteria; and
if the DRAM fails to meet said test criteria, then generating a new initial test instruction and restarting said self test of said DRAM. - View Dependent Claims (15, 16)
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17. A method of testing a memory, comprising the steps of:
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loading an initial self test instruction into a control register;
executing said self test instruction;
storing the results of executing said self test instruction;
determining from the stored results whether a memory meets test criteria; and
if the memory fails to meet said test criteria, then generating a new initial test instruction and restarting said self test of said memory.
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18. A method of self testing a chip, comprising:
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loading an initial self test instruction into a register;
executing said self test instruction;
storing the results of executing said self test instruction;
deciding from the results whether a chip meets test criteria; and
if the chip fails to meet said test criteria, then generating a new initial test instruction and restarting said self test.
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19. A method of testing a memory, comprising:
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providing a memory core;
providing a built in self test engine connected to control said memory core during a test condition;
providing a register for providing commands to said self test engine;
selectively providing a self-program circuit for providing commands to said register, and then testing the memory core.
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20. A method of testing a chip having a target circuit, comprising:
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providing a chip having a target circuit;
providing a built-in self test engine connected to control said target circuit during a test condition;
providing a register for providing commands to said engine, and selectively providing a self program circuit for providing commands to said register, and then testing the target circuit.
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Specification