Method of self programmed built in self test

• US 6,230,290 B1
• Filed: 07/02/1997
• Issued: 05/08/2001
• Est. Priority Date: 07/02/1997
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Heidel, David F., Hwang, Wei, Kirihata, Toshiaki
• Primary Examiner(s): Nguyen, Hoa T.
• Application Number:
  US08/887,462
• Time in Patent Office: 1,406 Days
• Field of Search: 714/718, 714/719, 714/724, 714/733, 714/734, 714/736, 365/201
• US Class Current: 714/718
• CPC Class Codes: G11C 29/16 using microprogrammed units, e.g. state machines

Abstract

A method of self-programmable Built In Self Test (BIST) for a memory (e.g., Dynamic Random Access Memory (DRAM)). The DRAM, which may be a DRAM chip, includes a DRAM core, a Microcode or Initial Command ROM, a BIST Engine, a Command Register and a Self-Program Circuit. During self test, the BIST engine may test the DRAM normally until an error is encountered. When an error is encountered, the Self-Program Circuit restarts the self test procedure at less stringent conditions. Optionally, when the DRAM tests error-free, the Self-Program Circuit may restart testing at more stringent conditions to determine DRAM functionality limits.

Claims

1. A method of testing a Dynamic Random Access Memory (DRAM), comprising:

providing a DRAM core;

providing a Built In Self Test (BIST) engine connected to control said DRAM core during a test condition;

providing a command register for providing control commands to said BIST engine;

providing a self-program circuit for selectively providing commands to said command register, and then testing the DRAM core with said commands.

2. The method of claim 1, wherein the BIST engine is configured to provide a test indication to said self-program circuit and said self program circuit is configured to provide commands to said command register responsive to said test indication.

3. The method of claim 2, further comprising providing an initial command store for providing initial commands of a test to said command register.

4. The method of claim 3, wherein the BIST engine comprises:

an address counter;

a instruction pointer;

a control signal generator for providing control signals to said DRAM and to said address counter;

a clock generator for supplying a clock signal to said control signal generator, said initial command store and said instruction pointer;

a data pattern generator for supplying test patterns to said DRAM core; and

,

a data comparator for comparing supplied patterns with data read from said DRAM core and for providing said test indication.

5. The method of claim 4, wherein the BIST engine further comprises a voltage control for selecting a test voltage of said DRAM core.

6. A method of testing a chip including said DRAM comprising the method of claim 5.

7. The method of claim 2, wherein the self-program circuit comprises:

a RAM, test indications being stored in said RAM; and

a microprocessor unit for interrogating said test indications, determining a next BIST instruction therefrom and providing said next BIST instruction to said command register, said microprocessor unit including a microprogram ROM for providing commands to said microprocessor.

8. A method of testing a DRAM chip, comprising:

providing a DRAM core;

providing a Built In Self Test (BIST) engine connected to supply control signals to said DRAM core;

providing an initial command store;

providing a command register for receiving commands from said initial command store and for providing control commands to said BIST engine;

providing a self-program circuit for selectively providing commands to said command register, and then testing the DRAM core with said commands.

9. The method of claim 8, wherein the initial command store is a Read Only Memory (ROM).

10. The method of claim 9, wherein the BIST engine is configured to provide a test indication to said self-program circuit and said self program circuit is configured to provide said commands to said command register responsive to said test indication.

11. The method of claim 10, said DRAM chip further comprising a test parameter monitor for monitoring at least one test parameter and for supplying test condition information to said self program circuit.

12. The method of claim 11, wherein the BIST engine comprises:

an address counter;

a instruction pointer;

a control signal generator for providing control signals to said DRAM and to said address counter;

a clock generator for supplying a clock signal to said control signal generator, said initial command store and said instruction pointer;

a data pattern generator for supplying test patterns to said DRAM core; and

a data comparator for comparing supplied patterns with data read from said DRAM core and for providing said test indication.

13. The method of claim 12, wherein the self-program circuit comprises:

a RAM, said test indication being stored in said RAM; and

a microprocessor unit for interrogating said test indications, determining a next BIST instruction therefrom and providing said next BIST instruction to said command register, said microprocessor unit including

a microprogram ROM providing commands to said microprocessor.

14. A method of self testing a DRAM, comprising the steps of:

loading an initial self test instruction into a control register;

executing said self test instruction;

storing the results of executing said self test instruction;

determining from the stored results whether a DRAM meets test criteria; and

if the DRAM fails to meet said test criteria, then generating a new initial test instruction and restarting said self test of said DRAM.

15. The method of claim 14, wherein if said DRAM fails to meet said test criteria, then said DRAM is tested under less severe test conditions.

16. The method of claim 14, wherein if said DRAM meets said test criteria, then said self test is restarted and said DRAM is tested under more severe test conditions.

17. A method of testing a memory, comprising the steps of:

loading an initial self test instruction into a control register;

executing said self test instruction;

storing the results of executing said self test instruction;

determining from the stored results whether a memory meets test criteria; and

if the memory fails to meet said test criteria, then generating a new initial test instruction and restarting said self test of said memory.

18. A method of self testing a chip, comprising:

loading an initial self test instruction into a register;

executing said self test instruction;

storing the results of executing said self test instruction;

deciding from the results whether a chip meets test criteria; and

if the chip fails to meet said test criteria, then generating a new initial test instruction and restarting said self test.

19. A method of testing a memory, comprising:

providing a memory core;

providing a built in self test engine connected to control said memory core during a test condition;

providing a register for providing commands to said self test engine;

selectively providing a self-program circuit for providing commands to said register, and then

testing the memory core.

20. A method of testing a chip having a target circuit, comprising:

providing a chip having a target circuit;

providing a built-in self test engine connected to control said target circuit during a test condition;

providing a register for providing commands to said engine, and

selectively providing a self program circuit for providing commands to said register, and then

testing the target circuit.