Method and apparatus for minimization of process defects while routing

• US 6,230,306 B1
• Filed: 04/17/1998
• Issued: 05/08/2001
• Est. Priority Date: 04/17/1998
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Scepanovic, Ranko, Andreev, Alexander E., Raspopovic, Pedja
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): DO, THUAN V
• Application Number:
  US09/062,310
• Time in Patent Office: 1,117 Days
• Field of Search: 395/500.14, 716/13
• US Class Current: 716/129
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

A method for optimizing the routing of nets in an integrated circuit device, said method comprising the steps of dividing an integrated circuit design with lines in a first direction and lines in a second direction, wherein said first direction is substantially orthogonal to said second direction, forming a routing graph with vertices corresponding to locations where lines in said first direction and lines in said second direction cross and edges connect vertices, for each edge in a plurality of edges in said routing graph, computing an individual edge occupancy value, for an edge in said plurality of edges, computing a penalty value as a function of the individual edge occupancy value of a different edge, and routing a net as a function of said penalty value.

Claims

1. A method for optimizing the routing of nets in an integrated circuit device, said method comprising:

a. dividing an integrated circuit design with lines in a first direction and lines in a second direction, wherein said first direction is substantially orthogonal to said second direction;

b. forming a routing graph with vertices corresponding to locations where lines in said first direction and lines in said second direction cross and with edges connecting the vertices;

c. for each of a plurality of the edges in said routing graph, computing an individual edge occupancy value, wherein the individual edge occupancy value is computed by determining at least one of a probability of a wire passing through said edge and a number of actual wires passing through said edge;

d. for an edge in said plurality of edges, computing a penalty value as a function of the individual edge occupancy value of a different edge; and

e. routing a net as a function of said penalty value.

2. The method of claim 1 wherein the edge for which the penalty value is computed is connected directly to said different edge.

3. The method of claim 1 further comprising the step of, for each edge in said plurality of edges, computing an individual capacity value.

4. The method of claim 3 wherein said penalty value is further computed as a function of the individual capacity value of said different edge.

5. The method of claim 4 wherein the penalty value is a function of the individual capacity value of the different edge divided by the individual occupancy value of the different edge.

6. The method of claim 4 wherein said penalty value is further a function of the individual occupancy value and the individual capacity value computed for the edge for which the penalty value is computed.

7. The method of claim 1 wherein the individual occupancy value of an edge is computed as a function of the potential occupancy of the edge.

8. The method of claim 1 wherein the individual occupancy value of an edge is computed as a function of the current occupancy of the edge.

9. The method of claim 1 wherein the individual occupancy value of an edge is computed as a function of both the current occupancy of the edge and the potential occupancy of the edge.

10. A method for distributing wires between layers in an integrated circuit design, said method comprising:

a. for a particular half-channel, marking grid lines in a first direction containing beginnings or ends of wires;

b. dividing said half-channel into strips based on the markings made in step a;

c. forming a routing graph that includes two vertices for each strip, wherein each of the two vertices corresponds to a different one of plural routing layers;

d. computing a capacity value for an edge between the two vertices corresponding to one of the strips; and

e. routing a net on said plural routing layers as a function of the capacity value.

11. The method of claim 10 wherein said plural routing layers comprise a first layer and a third layer, and wherein there is a second layer between said first and third layers.

12. The method of claim 11 wherein said capacity value is a function of the occupancy of a portion of the second layer.

13. A method according to claim 10 wherein the capacity value is constrained to be one of 0 and 1.

14. A method according to claim 10, wherein the layers corresponding to the two vertices are for routing wires in a same direction.

15. A method according to claim 10, wherein the capacity value is a function of the occupancy of a portion of a layer that lies between the layers to which the two vertices correspond.

16. An apparatus for optimizing the routing of nets in an integrated circuit device, said apparatus comprising:

a. means for dividing an integrated circuit design with lines in a first direction and lines in a second direction, wherein said first direction is substantially orthogonal to said second direction;

b. means for forming a routing graph with vertices corresponding to locations where lines in said first direction and lines in said second direction cross and with edges connecting the vertices;

c. means for, for each of a plurality of the edges in said routing graph, computing an individual edge occupancy value, wherein the individual edge occupancy value is computed by determining at least one of a probability of a wire passing through said edge and a number of actual wires passing through said edge;

d. means for, for an edge in said plurality of edges, computing a penalty value as a function of the individual edge occupancy value of a different edge; and

e. means for routing a net as a function of said penalty value.

17. The apparatus of claim 16 wherein the edge for which the penalty value is computed is connected directly to said different edge.

18. The apparatus of claim 16 further comprising means for, for each edge in said plurality of edges, computing an individual capacity value.

19. The apparatus of claim 18 wherein said penalty value is further computed as a function of the individual capacity value of said different edge.

20. The apparatus of claim 19 wherein the penalty value is a function of the individual capacity value of the different edge divided by the individual occupancy value of the different edge.

21. The apparatus of claim 20 wherein said penalty value is further a function of the individual occupancy value and the individual capacity value computed for the edge for which the penalty value is computed.

22. The apparatus of claim 16 wherein the individual occupancy value of an edge is computed as a function of the potential occupancy of the edge.

23. The apparatus of claim 16 wherein the individual occupancy value of an edge is computed as a function of the current occupancy of the edge.

24. The apparatus of claim 16 wherein the individual occupancy value of an edge is computed as a function of both the current occupancy of the edge and the potential occupancy of the edge.

25. An apparatus for distributing wires between layers in an integrated circuit design, said apparatus comprising:

a. for a particular half-channel, means for marking grid lines in a first direction containing beginnings or ends of wires;

b. means for dividing said half-channel into strips based on the markings made by means a;

c. means for forming a routing graph that includes two vertices for each strip, wherein each of the two vertices corresponds to a different one of plural routing layers;

d. means for computing a capacity value for an edge between the two vertices corresponding to one of the strips; and

e. means for routing a net on said plural routing layers as a function of the capacity value.

26. The apparatus of claim 25 wherein said plural routing layers comprise a first layer and a third layer, and wherein there is a second layer between said first and third layers.

27. The apparatus of claim 26 wherein said capacity value is a function of the occupancy of a portion of the second layer.

28. An apparatus according to claim 25 wherein the capacity value is constrained to be one of 0 and 1.

29. An apparatus according to claim 25, wherein the layers corresponding to the two vertices are for routing wires in a same direction.

30. An apparatus according to claim 25, wherein the capacity value is a function of the occupancy of a portion of a layer that lies between the layers to which the two vertices correspond.

31. A computer storage device with instructions thereon for optimizing the routing of nets in an integrated circuit device, said storage device comprising:

a. a computer encoded instruction for dividing an integrated circuit design with lines in a first direction and lines in a second direction, wherein said first direction is substantially orthogonal to said second direction;

b. a computer encoded instruction for forming a routing graph with vertices corresponding to locations where lines in said first direction and lines in said second direction cross and with edges connecting the vertices;

c. a computer encoded instruction for, for each of a plurality of the edges in said routing graph, computing an individual edge occupancy value, wherein the individual edge occupancy value is computed by determining at least one of a probability of a wire passing through said edge and a number of actual wires passing through said edge;

d. a computer encoded instruction for, for an edge in said plurality of edges, computing a penalty value as a function of the individual edge occupancy value of a different edge; and

e. a computer encoded instruction for routing a net as a function of said penalty value.