System and method for programming the hardware of field programmable gate arrays (FPGAs) and related reconfiguration resources as if they were software by creating hardware objects

• US 6,230,307 B1
• Filed: 01/26/1998
• Issued: 05/08/2001
• Est. Priority Date: 01/26/1998
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Edwards, Stephen G., Miller, Ian D., Harris, Jonathan C., Davis, Donald J., Bennett, Toby D.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Speight, Jibreel
• Application Number:
  US09/013,186
• Time in Patent Office: 1,198 Days
• Field of Search: 716/17, 716/16, 716/8, 703/23
• US Class Current: 716/116
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A method and system for programming the hardware of field programmable gate arrays and related reconfigurable resources as if they were software by creating hardware objects that implement application level functionalities, operating system functionalities, and hardware functionalities. Further controlling and executing the hardware objects via high level software constructs and managing the reconfigurable resources, such that the reconfigurable resources are optimized for the tasks currently executing.

Claims

1. A method of programming a field programmable gate array (FPGA), comprising the steps of:

providing a development environment which includes a hardware object generator, a text editor, a compiler, and a plurality of libraries;

defining a plurality of functional hardware units, each functional hardware unit defining a function that cannot be decomposed and including one or more logic elements;

storing said plurality of functional hardware units in a first one of said plurality of libraries;

generating a plurality of hardware objects with said hardware object generator, each said hardware object including one or more functional hardware units;

storing said plurality of hardware objects in said first library;

selecting one or more hardware objects with said text editor to define a unique function;

storing a plurality of said selected hardware objects or a plurality of references to said plurality of said selected hardware objects in a second one of said plurality of libraries, thereby creating a plurality of unique functions;

selecting one or more of said unique functions with said compiler to create a unique wrapper object module;

storing said wrapper object module in a third one of said plurality of libraries;

providing a runtime environment which includes a computing system and an interface between said computing system and the FPGA;

creating application software operable on said computing system wherein said application software comprises a selected set of hardware objects and said wrapper object modules; and

creating a plurality of hardware object instances, each of which is derived from a hardware object and is located at a physical location on the FPGA and each said hardware object instance being controlled by a respective wrapper object module.

2. The method according to claim 1, wherein said first selecting step further comprises the step of generating a software wrapper for each said selected hardware object to reference the hardware object, to provide a run access method, and to provide a mechanism to assign inputs and outputs.

3. The method according to claim 1, wherein said third storing step further comprises the steps of:

storing a plurality of references to said plurality of said selected hardware objects;

storing said plurality of unique functions in one of a plurality of files that comprise said second one of said plurality of libraries; and

retrieving said plurality of unique functions from one of a plurality of files that comprise said second one of said plurality of libraries.

4. The method according to claim 1, wherein said second selecting step further comprises the steps of:

compiling said unique functions stored in said plurality of files comprising said second one of said plurality of libraries; and

linking said unique functions stored in said plurality of files comprising said second one of said plurality of libraries with functions provided from additional said plurality of libraries.

5. The method according to claim 1, wherein said second selecting step further comprises the steps of:

creating a plurality of said unique wrapper object modules; and

storing a plurality of said wrapper object modules.

6. The method according to claim 1, wherein said second providing step further comprises a computing system comprised of a host processor and a reconfigurable processing unit.

7. The method according to claim 6, wherein said reconfigurable processing unit is comprised of a plurality of embedded processors and a plurality of FPGAs.

8. The method according to claim 7, wherein said operating system comprises an operating system that is adapted to run on said host processor and a reconfigurable operating system that is capable of running in said reconfigurable processing unit.

9. The method according to claim 7, wherein said operating system comprises an operating system that is adapted to run on said host processor and a reconfigurable operating system that is capable of running in said embedded processor.

10. The method according to claim 7, wherein said operating system comprises an operating system that is adapted to run on said host processor and a reconfigurable operating system that is capable of running in said host processor.

11. A method of operating a computer system comprising the steps of:

defining a plurality of hardware objects;

locating said hardware objects within the computing system to provide a set of functions;

executing said plurality of hardware objects within the computing system; and

swapping said plurality of hardware objects within the computing system to provide another set of functions.

12. The method according to claim 11, wherein said hardware objects are relocatable within said computing system.

13. The method according to claim 12, wherein said hardware objects are dynamically relocatable.

14. The method according to claim 11, wherein said defining step further comprises the steps of:

creating a plurality of functional hardware units, each functional hardware unit defining a function that cannot be decomposed and including one or more logic elements;

storing said functional hardware units in a reconfigurable object library; and

retrieving said functional hardware units from said reconfigurable object library.

15. The method according to claim 11, wherein said defining step further comprises the steps of:

creating pre-defined hardware objects;

storing said pre-defined hardware objects in a reconfigurable object library; and

retrieving said pre-defined hardware objects from said reconfigurable object library.

16. The method according to claim 11, wherein said defining step further comprises the steps of:

selecting a plurality of functional hardware units and a plurality of pre-defined hardware objects from a reconfigurable object library to perform said function or functions, each functional hardware unit defining a function that cannot be decomposed and including one or more logic elements;

coupling said functional hardware units into one or more said hardware objects; and

accessing a reconfigurable object library of said hardware objects, said functional hardware units, and said pre-defined hardware objects.

17. The method according to claim 11, wherein said defining step further comprises the steps of:

determining a standard structure for said hardware objects by specifying a standard size;

creating one or more standard interfaces for said hardware objects by specifying standard access methods; and

optimizing said standard size and standard access methods based on the specifications of the reconfigurable processing unit.

18. The method according to claim 17, wherein said optimizing step further comprises optimizing based on anticipated processing tasks to be executed on said reconfigurable processing unit.

19. The method according to claim 17, wherein said defining step further comprises the step of enforcing the use of said standard structures and said standard access methods.

20. The method according to claim 19, wherein said enforcing step further comprises the step of detecting and indicating errors in the use of said standard structures and said standard access methods.

21. The method according to claim 11, wherein said locating step further comprises the step of generating hardware object instances that implement the functionality specified by said hardware objects.

22. The method according to claim 16, wherein said coupling step further comprises combining a plurality of hardware objects into other hardware objects.

23. The method according to claim 11, wherein said swapping step further comprises the step of context switching.

24. The method of claim 11, wherein each hardware object requires a respective set of programmable resources of a programmable gate array, and collectively the hardware objects require more resources than are available on a programmable gate array, the method further comprising:

scheduling on the computer system as a function of programmable resource availability and programmable resource requirements of the hardware objects, times at which the hardware objects are to be loaded into the programmable gate array;

swapping said plurality of hardware objects between the programmable gate array and the computer system responsive to scheduled times for loading the hardware objects.

25. A method of operating a computer system, the method comprising the steps of:

defining a plurality of hardware objects;

locating said hardware objects within the computing system to provide a set of functions;

providing a plurality of wrapper object modules;

executing application software operable on said computing system wherein said application software comprises a selected set of said hardware objects and said wrapper object modules;

executing a plurality of hardware object instances, each of which is derived from a hardware object and is located at a physical location on one or more reconfigurable processing units and each said hardware object instance being controlled by a respective wrapper object module;

controlling the one or more reconfigurable processing units; and

swapping said plurality of hardware objects within the computing system to provide another set of functions.

26. The method of claim 25, wherein said controlling step further comprises the steps of:

scheduling one or more hardware objects;

instantiating said hardware objects as hardware object instances;

swapping said hardware object instances;

managing said hardware object instances;

directing the flow of data to and from said hardware object instances; and

collecting accounting information on system execution.

27. The method according to claim 26, wherein said scheduling step further comprises the step of accepting requests from multiple programs, multiple users, and multiple threads for said reconfigurable processing units.

28. The method according to claim 27, wherein said scheduling step further comprises the steps of:

arbitrating said requests for said reconfigurable processing units; and

implementing a resolution of said requests for said reconfigurable processing units.

29. The method according to claim 28, wherein said scheduling step further comprises the steps of:

accepting requests to change priorities for one or more hardware objects; and

queuing said requests for said hardware objects.

30. The method according to claim 29, wherein said instantiating step further comprises the step of loading said hardware object instances into said reconfigurable processing units.

31. The method according to claim 26, wherein said swapping step further comprises the step of context switching.

32. The method according to claim 31, wherein said context switching further comprises the steps of:

identifying functions composed of said hardware object instances which can be swapped out of said reconfigurable processing units;

selecting said hardware object instances based on a priority scheme, resource deadlock, or completion of one or more of said functions;

identifying functions composed of said hardware objects which can be swapped into said reconfigurable processing units;

selecting said hardware objects based on a priority scheme;

requesting said scheduling step to swap said hardware object instance out of said reconfigurable processing units;

swapping said hardware object instances out of said reconfigurable processing units;

requesting said scheduling step to swap said hardware object instances into said reconfigurable processing units; and

swapping said hardware object instances into said reconfigurable processing units.

33. The method according to claim 32, wherein said first swapping step further comprises the step of preserving the internal state of said hardware object instances if said hardware object instances were swapped out based on priority or resource deadlock.

34. The method according to claim 33, wherein said context switching step further comprises the steps of:

swapping a function into said reconfigurable processing units that had been previously swapped out of said reconfigurable processing units; and

commencing execution of said function at the point it was previously halted.

35. The method according to claim 26, wherein said directing step further comprises the steps of:

controlling one of said hardware object instances via its interface framework;

sending data to said hardware object instance via its interface framework; and

receiving data from said hardware object instance via its interface framework instance.

36. The method according to claim 26, wherein said collecting step comprises the steps of:

assembling said system execution information;

preserving said system execution information; and

reporting said system execution information.

37. A method of programming one or more intercoupled field programmable gate arrays (FPGAs) with a computer system coupled to the FPGAs, each FPGA comprising a plurality of programmable resources, comprising the steps of:

instantiating a plurality of hardware objects on the computer system, each hardware object requiring a respective set of programmable resources, and collectively, the hardware objects requiring more resources than are available on the one or more FPGAs;

scheduling on the computer system, as a function of programmable resource availability and programmable resource requirements of the hardware objects, times at which the hardware objects are to be loaded into the one or more FPGAs; and

loading the hardware objects into the one or more FPGAs at the scheduled times.

38. The method of claim 37, further comprising:

selecting a first set of one or more hardware objects to swap out of the one or more FPGAs, the first set of hardware objects presently loaded in a set of programmable resources of one or more FPGAs;

selecting a second hardware object instantiated on the computer system to swap in to the one or more FPGAs;

unloading the first hardware object from the one or more FGPAs; and

loading the second hardware object into set of programmable resources of the one or more FPGAs.

39. The method of claim 38, further comprising saving state data associated with the first set of one or more hardware objects prior to loading the second hardware object, whereby the state data is restorable to the one or more FPGAs when the first set of one or more hardware objects are reloaded.

40. The method of claim 38, further comprising:

maintaining in memory of the computer system a cache for temporary storage of selected ones of the hardware objects; and

storing the first hardware object in the cache upon unloading the first hardware object from the one or more FPGAS.

41. The method of claim 40, further comprising saving state data associated with the first set of one or more hardware objects prior to loading the second hardware object, whereby the state data is restorable to the one or more FPGAs when the first set of one or more hardware objects are reloaded.

42. The method of claim 38, further comprising:

dividing the programmable resources of the one or more FPGAs into a plurality of logical hardware pages, each page including a set of programmable resources; and

selecting the first set of one or more hardware objects to swap out of the one or more FPGAs as a function of a number of logical hardware pages required by the second hardware object and the number of logical hardware pages used by the first set of one or more hardware objects.

43. The method of claim 42, further comprising dividing the programmable resources of the one or more FPGAs into a plurality of logical hardware pages of one or more sizes, each size having a selected number of programmable logic elements.

44. The method of claim 37, wherein the scheduling step schedules the hardware objects as a function of respective time periods that the hardware objects have executed on the one or more FPGAs.

45. A system for operating a computer system comprising:

means for defining a plurality of hardware objects;

means for locating said hardware objects within the computing system to provide a set of functions;

means for executing said plurality of hardware objects within the computing system; and

means for swapping said plurality of objects within the computing system to provide another set of functions.

46. An apparatus for programming one or more intercoupled field programmable gate arrays (FPGAs) with a computer system coupled to the FPGAS, each FPGA comprising a plurality of programmable resources, comprising:

means for instantiating a plurality of hardware objects on the computer system, each hardware object requiring a respective set of programmable resources, and collectively the hardware objects requiring more resources than are available on the one or more FPGAs;

means for scheduling on the computer system, as a function of programmable resource availability and programmable resource requirements of the hardware objects, times at which the hardware objects are to be loaded into the one or more FPGAs; and

means for loading the hardware objects into the one or more FPGAs at the scheduled times.

47. A system for programming a field programmable gate array coupled to a computer system, the field programmable gate array having a plurality of programmable resources, the system for programming comprising:

a development subsystem including means for generating a plurality of executable hardware objects, each hardware object requiring a subset of the programmable resources;

a runtime subsystem adapted to receive and execute said plurality of hardware objects, the execution of said plurality of hardware objects resulting in a plurality of hardware object instances;

means for scheduling as a function of programmable resource availability and programmable resource requirements of the hardware object instances, times at which the hardware objects instances are to be loaded into the programmable crate array; and

means for swapping said plurality of hardware object instances between the programmable gate array and the computer system responsive to scheduled times for loading the hardware object instances.

48. The system according to claim 47, wherein said development subsystem further comprises:

means for defining a plurality of functional hardware units, each functional hardware unit defining a function that cannot be decomposed and including one or more logic elements;

means for storing said plurality of functional hardware units in one of said plurality of libraries;

means for retrieving said plurality of functional hardware units from one of said plurality of libraries;

means for storing said plurality of hardware objects in one of said plurality of libraries;

means for retrieving said plurality of hardware objects from one of said plurality of libraries;

means for creating a plurality of unique functions;

means for storing said plurality of unique functions in one of said plurality of libraries;

means for retrieving said plurality of unique functions from one of said plurality of libraries;

means for wrapping each of said plurality of unique functions to create a plurality of wrapper object modules;

means for storing said plurality of wrapper object modules in one of said plurality of libraries; and

means for retrieving said plurality of wrapper object modules from one of said plurality of libraries.

49. The system according to claim 47, wherein said runtime subsystem further comprises:

an application runtime environment;

a reconfigurable operating system (RCOS) application portability interface (API);

an RCOS; and

an FPGA.

50. The system according to claim 47, wherein said runtime subsystem further comprises:

means for interfacing between said FPGA and host system; and

means for creating application software operable on said FPGA wherein said application software comprises a selected set of hardware objects.

51. The system according to claim 49, wherein said RCOS further comprises:

a place and route layer; and

a device abstraction layer.

52. The system according to claim 49, wherein said FPGA further comprises:

a control interface;

a plurality of interface framework instances; and

a plurality of hardware object instances.

53. The system according to claim 51, wherein said RCOS further comprises:

means for controlling said plurality of hardware object instances on said FPGA;

means for managing data of said plurality of hardware object instances on said FPGA;

means for retrieving accounting information of said plurality of hardware object instances;

means for storing accounting information of said plurality of hardware object instances; and

means for reporting accounting information of said plurality of hardware object instances.

54. The system according to claim 51, wherein said place and route layer comprises:

means for placing and routing said plurality of hardware object instances on said FPGA;

means for instantiating said plurality of hardware object instances on said FPGA;

means for removing said plurality of hardware object instances from said FPGA;

means for collecting accounting information of said plurality of hardware object instances;

means for supplying data to said plurality of hardware object instances; and

means for receiving data from said plurality of hardware object instances.

55. The system according to claim 51, wherein said device abstraction layer further comprises:

means to interface to said FPGA; and

means to collect device specific information.