Process for forming a memory structure that includes NVRAM, DRAM, and/or SRAM memory structures on one substrate and process for forming a new NVRAM cell structure

• US 6,232,173 B1
• Filed: 09/23/1998
• Issued: 05/15/2001
• Est. Priority Date: 04/14/1997
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Mandelman, Jack Allan, Hsu, Louis Lu-Chen, Assaderaghi, Fariborz
• Primary Examiner(s): Pham, Long
• Assistant Examiner(s): Kebede, Brook
• Application Number:
  US09/159,470
• Time in Patent Office: 965 Days
• Field of Search: 438/211, 438/154, 438/152, 438/241, 438/253, 438/254, 438/244, 438/256, 438/597, 438/593, 438/592, 438/257, 438/238, 257/315, 257/379
• US Class Current: 438/253
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor memory device including an NVRAM cell structure, a DRAM cell structure, and an SRAM cell structure. The NVRAM cell structure, the DRAM cell structure, and the SRAM cell structure are on the same substrate. An NVRAM cell structure. Processes for forming a memory structure that includes NVRAM, DRAM, and/or SRAM memory structures on one substrate and processes for forming a new NVRAM cell structure.

Claims

1. A process of forming a DRAM cell structure, an NVRAM cell structure, and an SRAM cell structure, said process comprising the steps of:

providing a semiconductor substrate;

forming device isolation regions in said substrate;

forming n-well, p-well and threshold implant regions in said substrate;

forming a first dielectric layer over exposed areas of said substrate;

forming a first gate structure having a first layer of a conductive material aligned with source and drain regions on said substrate;

forming a first isolation region above said first gate structure;

forming first interconnections over source, drain or gate regions in said substrate;

forming a metallization on a top of said first interconnections;

forming a second isolation region above said first isolation region;

forming second interconnections over said first interconnections, said first gate structure, said first metallization, or said source or said drain regions;

forming a second layer of a conductive material on a top of said second interconnections;

forming a second dielectric layer on top of said second conductive layer; and

forming a third layer of a conductive material on top of said second layer of a dielectric material.

2. A process according to claim 1, wherein said first dielectric layer is a gate oxide formed by thermal oxidation, a CVD oxide or a CVD nitride.

3. A process according to claim 1, wherein said first layer of a conductive material forms a gate of a DRAM, SRAM, or NVRAM cell and is formed by a CVD polysilicon deposition.

4. A process according to claim 1, wherein said first isolation region is formed by a CVD oxide, a CVD TEOS, or a CVD glass.

5. A process according to claim 1, wherein said first interconnections are a CVD tungsten or a CVD doped polysilicon.

6. A process according to claim 1, wherein said second conductive layer is a doped CVD polysilicon and forms a node plate of a capacitor of a stacked capacitor DRAM cell.

7. A process according to claim 1, wherein said second conductive layer is a doped CVD polysilicon and forms the gate of a load pfet device for said SRAM cell structure and forms the upper floating gate of the NVRAM cell structure.

8. A process according to claim 1, wherein said second dielectric layer is formed with a thickness of about 40 Å

to about 100 Å

.

9. A process according to claim 1, wherein said third conductive layer is a doped CVD polysilicon and forms a ground plate of a capacitor of a stacked capacitor DRAM cell.

10. A process according to claim 1, wherein said third layer of a conductive material is a doped CVD polysilicon and forms a body of a load pfet device for said SRAM cell structure and a control gate of said NVRAM cell structure.

11. A process according to claim 1, wherein said second layer of conductive material is roughened.

12. A process for forming an NVRAM cell structure, said process comprising the steps of:

forming a source region in a substrate;

forming a drain region in said substrate;

forming an isolation region in said substrate adjacent each of said source region and said drain region;

forming a gate structure connected to said source region and said drain region, said gate structure including at least a first floating gate, an oxide layer being formed between said first floating gate and said source region and said drain region;

forming a first isolation region about said gate structure;

forming stud interconnections connected to said source region, said drain region, and said gate structure;

forming a first dielectric layer over exposed areas of said substrate and said gate structure;

forming a first metallization layer connected to said stud interconnections connected to said source region and said drain region;

forming an isolation layer over said first metallization layer;

forming a second floating gate of said NVRAM cell by depositing and patterning a doped polysilicon at least over said stud interconnection connected to said gate structure;

depositing a thin layer of a dielectric over said exposed surface of said doped polysilicon; and

forming a control gate of said NVRAM cell by depositing and patterning a doped polysilicon over said dielectric layer.

13. The process according to claim 12, wherein said exposed surface of the second floating gate is roughened.

14. The process for forming an NVRAM cell structure according to claim 12, wherein said process is compatible with a process for forming a DRAM cell structure and an SRAM cell structure.