Method of manufacturing floating gate of stacked-gate nonvolatile memory unit

• US 6,232,184 B1
• Filed: 09/10/1999
• Issued: 05/15/2001
• Est. Priority Date: 08/02/1999
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wang, Ling-Sung, Lin, Chingfu
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): PERT, EVAN T
• Application Number:
  US09/394,270
• Time in Patent Office: 613 Days
• Field of Search: 438/584, 438/585, 438/587, 438/588, 438/592, 438/593, 438/594, 438/595, 438/197, 438/257, 438/260, 438/264, 438/265
• US Class Current: 438/265
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure

Abstract

A method of manufacturing the floating gate of a stacked-gate type of nonvolatile memory unit. A gate oxide layer and a polysilicon layer are sequentially formed over a substrate. The polysilicon layer is etched to form a floating gate above the gate oxide layer. During the polysilicon etching operation, a polymeric material is also deposited on the sidewalls of the floating gate and over the exposed gate oxide. An isotropic chemical dry etching of the floating gate is carried out so that its bottom section is slightly wider than its top section. Finally, a thermal oxidation operation is carried out to form an oxide layer over the floating gate.

Claims

1. A method for manufacturing a gate electrode, comprising the steps of:

providing a substrate;

forming a gate oxide layer over the substrate;

forming a polysilicon layer over the gate oxide layer;

etching the polysilicon layer to form a gate electrode above the gate oxide layer and at the same time depositing polymeric material on sidewalls of the gate electrode and over the gate oxide layer;

performing a chemical dry etching operation to remove the plylmeric material and to shape the gate electrode; and

performing a thermal oxidation to form an oxide layer over the gate electrode.

2. The method of claim 1, wherein the step of etching the polysilicon layer includes reactive ion etching.

3. The method of claim 1, wherein the polysilicon layer is etched using gaseous etchants that include HBr, Cl₂, CF₄ and He/O₂.

4. The method of claim 3, wherein the polysilicon layer is etched at a pressure of between about 2 and 12 mtorr and gas flow rates for HBr, Cl₂, CF₄ and He/O₂ of about 80-200 sccm, 40-120 sccm, 1-40 sccm and 10-30 sccm, respectively.

5. The method of claim 3, wherein the ratio of helium to oxygen (the He/O₂ ratio) is about 7:

3.

6. The method of claim 1, wherein the chemical dry etching operation is carried out using a gaseous etchant containing halogen-containing gas and oxygen-containing gas.

7. The method of claim 6, wherein the halogen-containing gas and the oxygen containing gas are in a 1:

1 ratio.

8. The method of claim 6, wherein the gas flow rates of the halogen-containing gas and the oxygen-containing gas are both 20-500 sccm.

9. The method of claim 6, wherein the halogen-containing gas includes carbon tetrafluoride (CF₄).

10. The method of claim 6, wherein the oxygen-containing gas includes oxygen (O₂).

11. The method of claim 6, wherein the gaseous etchant further includes some inert gas as a diluent.

12. The method of claim 11, wherein the inert gas includes nitrogen (N₂).

13. The method of claim 12, wherein the inert gas has a flow rate of about 1-100 sccm.

14. A method for forming the floating gate of a stacked-gate type of nonvolatile memory unit, comprising the steps of:

providing a substrate having a gate oxide layer thereon;

forming a polysilicon layer over the gate oxide layer;

patterning the polysilicon layer to form a floating gate whose bottom section widens abruptly near the gate oxide layer, and

performing thermal oxidation to form an oxide layer over the floating gate.

15. The method of claim 14, wherein the step of patterning the polysilicon layer includes the substeps of:

etching the polysilicon layer to form a floating gate and at the same time depositing some polymeric material on the sidewalls of the floating gate and the gate oxide layer; and

performing chemical dry etching on the polymeric material and the floating gate.

16. The method of claim 15, wherein the polymeric material and the polysilicon layer are etched using gaseous etchants that include HBr, Cl₂, CF₄ and He/O₂.

17. The method of claim 15, wherein the chemical dry etching operation is carried out using a gaseous etchant containing halogen-containing gas and oxygen-containing gas.

18. The method of claim 17, wherein the halogen-containing gas and the oxygen-containing gas are in a 1:

1 ratio.

19. The method of claim 17, wherein the halogen-containing gas includes carbon tetrafluoride (CF₄).

20. The method of claim 17, wherein the oxygen-containing gas includes oxygen (O₂).

21. The method of claim 17, wherein the gaseous etchant further includes some inert gas as a diluent.

22. The method of claim 21, wherein the inert gas includes nitrogen (N₂).