Method for fabricating a radio frequency power MOSFET device having improved performance characteristics

• US 6,232,186 B1
• Filed: 03/23/2000
• Issued: 05/15/2001
• Est. Priority Date: 10/31/1997
• Status: Expired due to Term

• Current Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Patel, Viren C.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): ANYA, IGWE U
• Application Number:
  US09/534,434
• Time in Patent Office: 418 Days
• Field of Search: 438/268, 438/433, 438/522, 438/542
• US Class Current: 438/268
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: Y10S 438/931 Silicon carbide semiconductor

Abstract

A power MOSFET suitable for use in RF applications and a method for making the same is disclosed. The power MOSFET reduces the gate coverage of the drain region of the device in order to decrease the device gate to drain capacitance C_gd. A significant portion of the gate overlaying the drain region is eliminated by the removal of a portion of a polysilicon layer that is disposed over a substantial portion of the drain region that resides between the channel portions of the body regions of the device. The resulting open area, that is subsequently covered by an oxide layer, separates the polysilicon gate electrodes of the device. Finally, a metal layer is deposited over the entire structure to form the gate and source electrodes of the device.

Claims

1. Forming a vertical MOSFET device, comprising the steps of:

forming a semiconductor substrate having first and second opposing major surfaces;

growing a first oxide layer on the first surface;

depositing polysilicon on the first oxide layer;

doping the polysilicon;

defining a polysilicon layer from the doped polysilicon;

forming a body region of second conductivity type extending into the substrate and under the polysilicon layer from the first surface and defining a drain region having an extended drain portion bounded by the body region;

forming a source region of first conductivity type extending into the substrate from the first surface within the boundaries of the body region;

forming a channel portion, defined at the first surface by the source region and the extended drain portion, wherein the polysilicon layer overlays a portion of the source region, the channel portion, and at least a portion of the extended drain portion adjacent the channel portion;

forming a drain electrode contacting the drain region on the second surface;

placing a photo resist over a first portion of the polysilicon layer that is disposed over a portion of the source region, the channel region, and at least a portion of the extended drain portion adjacent the channel portion but not over the entire extended drain portion, wherein the first portion of the polysilicon layer is a polysilicon gate electrode that corresponds to the channel portion;

removing a second portion of the polysilicon layer that is not protected by the photo resist;

removing the photo resist over the polysilicon gate electrode;

growing a second oxide layer disposed over the polysilicon gate electrode and the first oxide layer;

forming a first window in the second oxide layer over the polysilicon gate electrode so as to expose a top surface of the polysilicon gate electrode; and

placing a layer of metal in the first window in the second oxide layer over the polysilicon gate electrode to form a metal gate electrode having electrical contact with the polysilicon gate electrode.

2. The method of claim 1, wherein after the step of growing a second oxide layer and prior to the step of placing the layer of metal, comprising the additional steps of:

forming a second window in the second oxide layer over the source region so as to expose the source region; and

simultaneous with forming the metal gate electrode, placing the metal layer in the second window in the second oxide layer to form a source electrode contacting the source region.

3. A method for forming a vertical MOSFET device, comprising the steps of:

forming a semiconductor substrate having first and second opposing major surfaces;

growing a first oxide layer on the first surface;

depositing polysilicon on the first oxide layer;

doping the polysilicon;

defining a polysilicon layer from the doped polysilicon;

forming a first body region and a second body region of second conductivity type extending into the substrate and under the polysilicon layer from the first surface and defining a drain region having an extended drain portion bounded by the first and second body regions;

forming a first source region and a second source region of first conductivity type, the first source region extending into the substrate from the first surface within the boundary of the first body region and the second source region extending into the substrate from the first surface within the boundary of the second body region;

forming a first channel portion and a second channel portion, defined at the first surface by the first and second source regions and the extended drain portion therebetween, wherein the polysilicon layer overlays a portion of the first and second source regions, the first and second channel portions, and at least a portion of the extended drain portion adjacent the first and second channel portions;

forming a drain electrode contacting the drain region on the second surface;

placing photo resist over first and second portions of the polysilicon layer, wherein the first portion of the polysilicon layer is disposed over a portion of the first source region, the first channel portion, and at least a portion of the extended drain portion adjacent the first channel portion but not over the entire extended drain portion adjacent the first channel portion and the second portion of the polysilicon layer is disposed over a portion of the second source region, the second channel portion, and at least a portion of the extended drain portion adjacent the second channel portion but not over the entire extended drain portion adjacent the second channel portion and wherein the first portion of the polysilicon layer is a first polysilicon gate electrode corresponding to the first channel portion and the second portion of the polysilicon layer is a second polysilicon gate electrode corresponding to the second channel portion;

removing a third portion of the polysilicon layer that is not protected by the photo resist and that is disposed between the first and second portions of the polysilicon layer to form an opening on the first oxide layer between the first and second portions of the polysilicon layer;

removing the photo resist over the first and second polysilicon gate electrodes;

growing a second oxide layer disposed over the first and second polysilicon gate electrodes and the first oxide layer;

forming first and second windows in the second oxide layer over the first and second polysilicon gate electrodes so as to expose a top surface of the first and second polysilicon gate electrodes; and

placing a layer of metal in the first and second windows in the second oxide layer over the first and second polysilicon gate electrodes to form first and second metal gate electrodes having electrical contact with the first and second polysilicon gate electrodes.

4. The method of claim 3, wherein after the step of growing a second oxide layer and prior to the step of placing the layer of metal, comprising the additional steps of:

forming third and fourth windows in the second oxide layer over the first and second source regions so as to expose the first and second source regions; and

simultaneous with forming the first and second metal gate electrodes, placing the metal layer in the third and fourth windows in the second oxide layer to form a first and second source electrodes contacting the first and second source regions.