Flip chip bump bonding

• US 6,232,212 B1
• Filed: 02/23/1999
• Issued: 05/15/2001
• Est. Priority Date: 02/23/1999
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Degani, Yinon, Kossives, Dean Paul
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Vu, David
• Application Number:
  US09/256,443
• Time in Patent Office: 812 Days
• Field of Search: 438/612, 438/613, 438/614, 438/615, 438/584, 438/597
• US Class Current: 438/612
• CPC Class Codes: H01L 2224/03912 the bump being used as a mask for patterning the bonding area
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01011 : Sodium [Na]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

The specification describes techniques for applying solder bumps to IC chips. The solder bump sites are first provided with under bump metallization (UBM) for solder bump interconnections to the Al bonding sites on the IC chip. The substrate, i.e. the capping layer of the IC chip, is coated with photoresist and patterned to expose the UBM and a peripheral portion of the capping layer around the UBM. The solder paste is then applied and reflowed to form the solder bump. Since the photoresist hardens and becomes difficult to remove after the reflow step, a sacrificial buffer layer is interposed between the photoresist and the capping layer to facilitate removal of the photoresist without attacking the IC chip surface.

Claims

1. A process for bonding an IC chip to a support substrate, said IC chip having a a plurality of aluminum bonding sites and a capping layer surrounding the plurality of aluminum bonding sites, comprising the steps of:

(a) selectively applying under bump metallization (UBM) to the aluminum bonding sites, leaving portions of the capping layer exposed,

(b) forming a buffer layer directly on the said portions of the capping layer,

(c) forming a photoresist mask on said buffer layer, said photoresist mask having open portions thereof exposing said UBM,

(d) filling said open portions of the photoresist mask with solder paste,

(e) heating said solder paste to reflow the solder paste and form solder bumps on said UBM,

(f) removing said photoresist mask, and

(g) removing said buffer layer.

2. The process of claim 1 wherein a portion of said buffer layer is part of said UBM.

3. The process of claim 2 wherein said UBM is a layered structure comprising at least two metal layers, and one of said metal layers extends over said capping layer to form said buffer layer.

4. The process of claim 3 wherein said UBM is a layered structure comprising Ti, Cr/Cu,Cu, and the titanium layer extends over said capping layer to form said buffer layer.

5. The process of claim 1 wherein said capping layer is polyimide.

6. The method of claim 1 wherein the buffer layer is selected from the group consisting of titanium, aluminum, molybdenum, and tungsten.

7. A process for bonding an IC chip to a support substrate, said IC chip having a plurality of aluminum bonding sites and a capping layer surrounding the plurality of aluminum bonding sites, comprising the steps of:

(a) depositing under bump metallization (UBM) on the IC chip, the UBM comprising at least two metal layers, a first metal layer deposited on the capping layer, and a second metal layer deposited on the first metal layer,

(b) patterning the second metal layer to cover at least a portion of said aluminum bonding sites, leaving portions of the first metal layer exposed,

(c) forming a photoresist mask on said portions of the first metal layer, said photoresist mask having open portions thereof exposing said UBM,

(e) filling said open portions of the photoresist mask with solder paste,

(f) heating the solder paste to reflow the solder paste to form solder bumps on said UBM,

(g) removing said photoresist mask, and

(h) removing said portions of the first metal layer.

8. The process of claim 7 wherein the first metal layer comprises a metal that is not wettable with the solder.

9. The method of claim 8 wherein the first metal layer is selected from the group consisting of titanium, aluminum, molybdenum, and tungsten.

10. The process of claim 7 wherein open portions of said photoresist mask expose a peripheral region of said buffer layer surrounding said UBM layer.

11. A process for bonding an IC chip to a support substrate, said IC chip having a plurality of aluminum bonding sites and a capping layer surrounding the plurality of aluminum bonding sites, comprising the steps of:

(a) selectively applying under bump metallization (UBM) to the aluminum bonding sites, leaving portions of the capping layer exposed,

(b) blanket depositing a metal layer on said portions of the capping layer and said UBM,

(c) forming a photoresist mask on said metal layer, said photoresist mask having open portions thereof exposing said metal layer over said UBM,

(d) etching away the metal layer over said UBM, using said patterned photoresist mask as an etch mask,

(e) filling said open portions of the photoresist mask with solder paste,

(f) heating the solder paste to reflow the solder paste and form solder bumps on said UBM,

(g) removing said photoresist mask, and

(h) removing said metal layer.

12. The process of claim 11 wherein the first UBM layer comprises a material that is not wettable with the solder.

13. The process of claim 12 wherein said capping layer comprises polyimide.

14. The process of claim 11 wherein open portions of said photoresist mask expose a peripheral region of said capping layer surrounding said UBM.

15. The method of claim 12 wherein the metal layer is selected from the group consisting of titanium, aluminum, molybdenum, and tungsten.