Semiconductor interconnect interface processing by high temperature deposition

• US 6,232,230 B1
• Filed: 01/05/1999
• Issued: 05/15/2001
• Est. Priority Date: 01/05/1999
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Iacoponi, John A.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Nhu, David
• Application Number:
  US09/227,067
• Time in Patent Office: 861 Days
• Field of Search: 438/619, 438/624, 438/627, 438/637, 438/638, 438/639, 438/640, 438/678, 438/687, 438/688, 438/660, 438/692, 438/626, 438/628, 438/633, 438/693, 438/697, 438/748, 438/653
• US Class Current: 438/687
• CPC Class Codes: H01L 21/7681 involving one or more buried masks
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76858 by diffusing alloying elements

Abstract

A method is provided for forming adhesion/barrier/conductor layers on semiconductor wafers in vias by using a high temperature adhesion/barrier material deposition step. The adhesion/barrier material is deposited over a channel conductor in the semiconductor dielectric with the semiconductor wafer at high temperature over 400° C., the temperature is reduced below 150° C., and then seed material is deposited so it is not exposed to temperatures above 150° C. which cause agglomeration.

Claims

1. A method of manufacturing a semiconductor device, comprising the steps of:

providing a semiconductor wafer with a first dielectric layer formed thereon;

forming an opening in said first dielectric layer, said opening defined by walls of said first dielectric layer;

filling said opening with a conductive material;

forming a second dielectric layer on said first dielectric layer;

forming an opening in said second dielectric layer, said opening defined by walls of said second dielectric layer and connected to said conductive material;

forming an adhesion/barrier layer to line said second dielectric layer in said opening and in contact with said conductive material, said forming of said adhesion/barrier layer performed at a high temperature whereby intermixing of said conductive material and said adhesion/barrier layer occurs;

cooling and adhesion/barrier layer to a temperature below a temperature at which seed material agglomerates; and

forming a seed layer of said seed material to line said adhesion/barrier layer at a temperature below said agglomeration temperature.

2. The method as claimed in claim 1 wherein the step of heating said semiconductor wafer increases the temperature thereof sufficiently to cause intermixing and insufficiently to cause agglomeration of said conductive material.

3. The method as claimed in claim 1 wherein the step of heating said semiconductor wafer is performed at temperatures at and above 400°

C.

4. The method as claimed in claim 1 including the step of cooling said semiconductor wafer to below 150°

C. during said step of forming said seed layer.

5. The method as claimed in claim 1 wherein the step of forming said adhesion/barrier layer uses a high temperature deposition technique selected from a group comprising ion metal plasma, collimated physical vapor deposition, other physical vapor deposition, chemical vapor deposition, and a combination thereof.

6. The method as claimed in claim 1 wherein the step forming said adhesion/barrier layer uses a material selected from a group comprising tantalum, titanium, tungsten, alloys thereof, and combinations thereof.

7. The method as claimed in claim 1 wherein the step of forming said seed layer uses a material selected from a group comprising copper, aluminum, silver, gold, alloys thereof, and combinations thereof.

8. The method as claimed in claim 1 wherein the step of filling said opening with a conductive material uses a material selected from a group comprising copper, aluminum, silver, gold, alloys thereof, and combinations thereof.

9. A method of manufacturing a semiconductor device, comprising the steps of:

providing a semiconductor wafer with a first dielectric layer formed thereon;

forming an opening in said first dielectric layer, said opening defined by walls of said first dielectric layer;

filling said opening with a conductive material selected from a group comprising copper, copper alloys, and a combination thereof;

forming a second dielectric layer on said first dielectric layer;

forming an opening in said second dielectric layer, said opening defined by walls of said second dielectric layer and connected to said conductive material;

heating said semiconductor wafer to above the agglomeration temperature of said conductive material;

deposing an adhesion/barrier layer to line said dielectric layer in said opening and in contact with said conductive material during said heating step whereby intermixing of said conductive material and said adhesion/barrier layer occurs, said adhesion/barrier layer selected from a group comprising tantalum, tantalum alloys, and a combination thereof;

cooling said adhesion/barrier layer to a temperature below a temperature at which seed material agglomerates; and

depositing a seed layer of said seed material to line said adhesion/barrier layer at a temperature below said agglomeration temperature, said seed layer selected from a group comprising copper, copper alloys, and a combination thereof.

10. The method as claimed in claim 9 wherein the step of heating said semiconductor wafer increases the temperature thereof sufficiently to cause said intermixing and insufficiently to cause difficulty manufacturing other semiconductor devices on said semiconductor wafer.

11. The method as claimed in claim 9 wherein the step of heating said semiconductor wafer increases the temperature thereof sufficiently to cause said intermixing to form an intermixed region about and below 30 angstroms in thickness.

12. The method as claimed in claim 9 wherein the step of heating said semiconductor wafer is performed at temperatures at and above 400°

C.

13. The method as claimed in claim 9 including the step of cooling said semiconductor wafer to below 150°

C. before said step of depositing said seed layer.

14. The method as claimed in claim 9 wherein the step of heating said semiconductor wafer uses a high temperature deposition technique selected from a group comprising ion metal plasma, collimated physical vapor deposition, other physical vapor deposition, chemical vapor deposition, and a combination thereof.