Trench photosensor for a CMOS imager

• US 6,232,626 B1
• Filed: 02/01/1999
• Issued: 05/15/2001
• Est. Priority Date: 02/01/1999
• Status: Expired due to Term

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Rhodes, Howard E.
• Primary Examiner(s): NGO, NGAN V
• Application Number:
  US09/241,080
• Time in Patent Office: 834 Days
• Field of Search: 257/290, 257/291, 257/292, 257/436, 257/448, 257/461, 257/462, 257/465, 257/466
• US Class Current: 257/292
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14689 MOS based technologies

Abstract

A trench photosensor for use in a CMOS imager having an improved charge capacity. The trench photosensor may be either a photogate or photodiode structure. The trench shape of the photosensor provides the photosensitive element with an increased surface area compared to a flat photosensor occupying a comparable area on a substrate. The trench photosensor also exhibits a higher charge capacity, improved dynamic range, and a better signal-to-noise ratio. Also disclosed are processes for forming the trench photosensor.

Claims

1. A photosensor for use in an imaging device, said photosensor comprising:

a doped layer of a first conductivity type formed in a substrate;

a trench formed in said doped layer;

a doped region of a second conductivity type formed at the sidewalls and bottom of said trench; and

an insulating layer formed over said doped region.

2. The photosensor of claim 1, wherein the photosensor is a photodiode sensor.

3. The photosensor of claim 2, wherein the insulating layer has a thickness of at least 30 Angstroms.

4. The photosensor of claim 1, wherein the trench has a depth within the range of approximately 0.05 to 10 μ

m.

5. The photosensor of claim 1, further comprising a conductive layer formed on substantially all of an upper surface of said insulating layer for gating the collection of charges in said doped region.

6. The photosensor of claim 5, wherein the insulating layer has a thickness within the range of approximately 20 to 500 Angstroms.

7. The photosensor of claim 5, wherein the photosensor is a photogate sensor.

8. The photosensor of claim 5, wherein the conductive layer is a doped polysilicon layer.

9. The photosensor of claim 5, wherein the conductive layer is a layer of indium tin oxide.

10. The photosensor of claim 5, wherein the conductive layer is a layer of tin oxide.

11. The photosensor of claim 5, wherein the conductive layer is a doped layer of a second conductivity type.

12. The photosensor of claim 5, wherein the conductive layer is substantially transparent to light radiation.

13. The photosensor of claim 5, wherein the conductive layer has a thickness within the range of approximately 200 to 4000 Angstroms.

14. The photosensor of claim 1, wherein the insulating layer is a silicon dioxide layer.

15. The photosensor of claim 1, wherein the insulating layer is a silicon nitride layer.

16. The photosensor of claim 1, wherein the insulating layer is a layer of ONO.

17. The photosensor of claim 1, wherein the insulating layer is a layer of ON.

18. The photosensor of claim 1, wherein the insulating layer is a layer of NO.

19. The photosensor of claim 1, wherein the first conductivity type is p-type, and the second conductivity type is n-type.

20. The photosensor of claim 1, wherein the doped region is formed by a process of multiple angled ion implantation.

21. The photosensor of claim 20, wherein the process comprises four orthogonal angled implants at a dose of 1×

10¹² to 1×

10¹⁶ ions/cm², wherein a resist is placed on top of the substrate while implanting, and wherein the angle of implantation for each angled implant is greater than θ

_C, where tan θ

_C=[(t+d)/(w)], where t is the thickness of the resist, d is the depth of the trench, and w is the width of the trench.

22. The photosensor of claim 21, wherein the dose of each implant is 1×

10¹³ to 1×

10¹⁵ ions/cm².

23. The photosensor of claim 21, wherein the dose of each implant is 5×

10¹³ ions/cm².

24. A photogate sensor for use in an imaging device, said photogate sensor comprising:

a doped layer of a first conductivity type formed in a substrate;

a trench formed in said doped layer;

a doped region of a second conductivity type formed at the sidewalls and bottom of said trench;

an insulating layer formed on substantially all of an upper surface of said doped region; and

a light radiation-transparent electrode formed on substantially all of an upper surface of said insulating layer for gating the collection of charges in said doped region.

25. The photogate sensor of claim 24, wherein the trench has a depth within the range of approximately 0.05 to 10 μ

m.

26. The photogate sensor of claim 24, wherein the first conductivity type is p-type, and the second conductivity type is n-type.

27. The photogate sensor of claim 24, wherein the insulating layer has a thickness within the range of approximately 20 to 500 Angstroms.

28. The photogate sensor of claim 24, wherein the insulating layer is a layer of silicon dioxide.

29. The photogate sensor of claim 24, wherein the insulating layer is a layer of silicon nitride.

30. The photogate sensor of claim 24, wherein the insulating layer is a layer of ONO.

31. The photogate sensor of claim 24, wherein the insulating layer is a layer of ON.

32. The photogate sensor of claim 24, wherein the insulating layer is a layer of NO.

33. The photogate sensor of claim 24, wherein the radiation-transparent electrode has a thickness within the range of approximately 200 to 4000 Angstroms thick.

34. The photogate sensor of claim 24, wherein the radiation-transparent electrode is a layer of doped polysilicon.

35. The photogate sensor of claim 24, wherein the radiation-transparent electrode is a layer of indium tin oxide.

36. The photogate sensor of claim 24, wherein the radiation-transparent electrode is a layer of tin oxide.

37. The photogate sensor of claim 24, wherein the radiation-transparent electrode is doped to a second conductivity type.

38. The photogate sensor of claim 37, wherein the first conductivity type is p-type, and the second conductivity type is n-type.

39. The photogate sensor of claim 24, wherein the doped region is formed by a process of multiple angled ion implantation.

40. The photogate sensor of claim 39, wherein the process comprises four orthogonal angled implants at a dose of 1×

10¹² to 1×

10¹⁶ ions/cm², wherein a resist is placed on top of the substrate while implanting, and wherein the angle of implantation for each angled implant is greater than θ

_C, where tan θ

_C=[(t+d)/(½

w)], where t is the thickness of the resist, d is the depth of the trench, and w is the width of the trench.

41. The photogate sensor of claim 40, wherein the dose of each implant is 1×

10¹³ to 1×

10¹⁵ ions/cm².

42. The photogate sensor of claim 40, wherein the dose of each implant is 5×

10¹³ ions/cm².

43. A photodiode sensor for use in an imaging device, said photodiode sensor comprising:

a doped layer of a first conductivity type formed in a substrate;

a trench formed in said doped layer, wherein the trench has a depth within the range of approximately 0.05 to 10 μ

m; and

a doped region of a second conductivity type formed at the sidewalls and bottom of said trench.

44. The photodiode sensor of claim 43, wherein the first conductivity type is p-type and the second conductivity type is n-type.

45. The photodiode sensor of claim 43, wherein the doped region is formed by a process of multiple angled ion implantation.

46. The photodiode sensor of claim 45, wherein the process comprises four orthogonal angled implants at a dose of 1×

10¹² to 1×

10¹⁶ ions/cm², wherein a resist is placed on top of the substrate while implanting, and wherein the angle of implantation for each angled implant is greater than θ

_C, where tan θ

_C=[(t+d)/(w)], where t is the thickness of the resist, d is the depth of the trench, and w is the width of the trench.

47. The photodiode sensor of claim 46, wherein the dose of each implant is 1×

10¹³ to 1×

10¹⁵ ions/cm².

48. The photodiode sensor of claim 46, wherein the dose of each implant is 5×

10¹³ ions/cm².

49. A pixel sensor cell for use in an imaging device, said pixel sensor cell comprising:

a doped layer of a first conductivity type formed in a substrate;

a trench formed in said doped layer;

a first doped region of a second conductivity type formed at the sidewalls and bottom of said trench;

an insulating layer formed over said first doped region;

a second doped region of a second conductivity type formed in said doped layer and positioned to receive charges from said first doped region of said trench; and

a reset transistor formed at the doped layer for periodically resetting a charge level of said second doped region, said second doped region being the source of said reset transistor.

50. The pixel sensor cell of claim 49, wherein the pixel sensor cell is a photodiode sensor cell.

51. The pixel sensor cell of claim 50, wherein the insulating layer has a thickness of at least 30 Angstroms.

52. The pixel sensor cell of claim 49, further comprising a conductive layer formed on substantially all of an upper surface of said insulating layer for gating the collection of charges in said first doped region.

53. The pixel sensor cell of claim 52, wherein the insulating layer has a thickness within the range of approximately 20 to 500 Angstroms.

54. The pixel sensor cell of claim 52, wherein said conductive layer is a layer of indium tin oxide.

55. The pixel sensor cell of claim 52, wherein said conductive layer is a layer of tin oxide.

56. The pixel sensor cell of claim 52, wherein said conductive layer is a layer of doped polysilicon.

57. The pixel sensor cell of claim 52, wherein the pixel sensor cell is a photogate sensor cell.

58. The pixel sensor cell of claim 52, further comprising a transfer gate formed on the doped layer between the trench and the second doped region.

59. The pixel sensor cell of claim 58, wherein said conductive layer extends over a top surface of the transfer gate.

60. The pixel sensor cell of claim 58, wherein said insulating layer extends over the top surface of the transfer gate.

61. The pixel sensor cell of claim 52, wherein said conductive layer is substantially transparent to radiation.

62. The pixel sensor cell of claim 52, wherein said conductive layer is a layer of doped polysilicon.

63. The pixel sensor cell of claim 49, wherein said insulating layer is a layer of silicon dioxide.

64. The pixel sensor cell of claim 49, wherein the first conductivity type is p-type, and the second conductivity type is n-type.

65. The pixel sensor cell of claim 49, wherein the first doped region is formed by a process of multiple angled ion implantation.

66. The pixel sensor cell of claim 65, wherein the process comprises four orthogonal angled implants at a dose of 1×

10¹² to 1×

10¹⁶ ions/cm², wherein a resist is placed on top of the substrate while implanting, and wherein the angle of implantation for each angled implant is greater than θ

_C, where tan θ

_C=[(t+d)/(w)], where t is the thickness of the resist, d is the depth of the trench, and w is the width of the trench.

67. The pixel sensor cell of claim 66, wherein the dose of each implant is 1×

10¹³ to 1×

10¹⁵ ions/cm².

68. The pixel sensor cell of claim 66, wherein the dose of each implant is 5×

10¹³ ions/cm².

69. A pixel sensor cell for use in an imaging device, said pixel sensor cell comprising:

a doped layer of a first conductivity type formed in a substrate;

a trench formed in said doped layer;

a photodiode formed in said trench, wherein said photodiode comprises a first doped region of a second conductivity type formed at the sidewalls and bottom of said trench, and an insulating layer formed on an upper surface of said first doped region;

a second doped region of a second conductivity type formed in said doped layer and positioned to receive charges from said first doped region of said trench; and

a reset transistor formed at the doped layer for periodically resetting a charge level of said second doped region, said second doped region being the source of said reset transistor.

70. A pixel sensor cell for use in an imaging device, said pixel sensor cell comprising:

a doped layer of a first conductivity type formed in a substrate;

a trench formed in said doped layer;

a photogate formed in said trench, wherein said photogate comprises a first doped region of a second conductivity type formed at the sidewalls and bottom of said trench, a conductive layer formed on substantially all of an upper surface of said first doped region for gating the collection of charges in said first doped region, and an insulating layer formed between said first doped region and said conductive layer;

a second doped region of a second conductivity type formed in said doped layer and positioned to receive charges from said first doped region of said trench; and

a reset transistor formed at the doped layer for periodically resetting a charge level of said second doped region, said second doped region being the source of said reset transistor.

71. A pixel sensor cell for use in an imaging device, said pixel sensor cell comprising:

a trench photosensor formed in a doped layer of a first conductivity type of a substrate;

a reset transistor formed in said doped layer;

a floating diffusion region of a second conductivity type formed in said doped layer between the trench photosensor and the reset transistor for receiving charges from said trench photosensor, said reset transistor operating to periodically reset a charge level of said floating diffusion region; and

an output transistor having a gate electrically connected to the floating diffusion region.

72. The pixel sensor cell of claim 71, wherein the trench photosensor further comprises a doped region of a second conductivity type located on the sidewalls and bottom of said trench.

73. The pixel sensor cell of claim 71, wherein the trench photosensor is a photodiode sensor.

74. The pixel sensor cell of claim 71, further comprising a transfer gate located between the trench photosensor and the floating diffusion region.

75. The pixel sensor cell of claim 74, wherein the trench photosensor is a photogate sensor.

76. The pixel sensor cell of claim 71, wherein the first conductivity type is p-type, and the second conductivity type is n-type.

77. A CMOS imager comprising:

a substrate having a doped layer of a first conductivity type;

an array of pixel sensor cells formed in said doped layer, wherein each pixel sensor cell has a trench photosensor; and

signal processing circuitry electrically connected to receive and process output signals from said array.

78. The CMOS imager of claim 77, wherein the trench photosensor further comprises a doped region of a second conductivity type located on the sidewalls and bottom of said trench.

79. The CMOS imager of claim 78, wherein the second conductivity type is n-type.

80. The CMOS imager of claim 77, wherein the trench photosensors are photodiode sensors.

81. The CMOS imager of claim 77, wherein the trench photosensors are photogate sensors.

82. The CMOS imager of claim 77, wherein the first conductivity type is p-type.

83. An integrated circuit imager comprising:

an array of pixel sensor cells formed in a substrate, wherein each pixel sensor cell has a trench photosensor;

signal processing circuitry formed in said substrate and electrically connected to the array for receiving and processing signals representing an image output by the array and for providing output data representing said image; and

a processor for receiving and processing data representing said image.

84. An integrated circuit imager comprising:

a CMOS imager, said CMOS imager comprising an array of pixel sensor cells formed in a doped layer on a substrate, wherein each pixel sensor cell has a trench photosensor with a first doped region formed therein, each of said cells having a respective second doped region for receiving and outputting image charge received from said first doped region, and signal processing circuitry formed in said substrate and electrically connected to the array for receiving and processing signals representing an image output by the array and for providing output data representing said image; and

a processor for receiving and processing data representing said image.