Non-volatile memory cell and method for manufacturing same

• US 6,232,634 B1
• Filed: 07/29/1998
• Issued: 05/15/2001
• Est. Priority Date: 07/29/1998
• Status: Expired due to Term

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Swift, Craig Thomas, Shum, Danny P., Wu, Yun-Kang (Kevin) K.
• Primary Examiner(s): Jackson, Jr., Jerome
• Application Number:
  US09/124,592
• Time in Patent Office: 1,021 Days
• Field of Search: 257/320, 257/321, 257/315, 257/316, 365/187, 365/185.05, 365/185.11, 365/185.26
• US Class Current: 257/316
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A non-volatile memory cell (81) includes a drain-side select transistor (86), a source-side select transistor (87), and a storage transistor (88). The drain-side select transistor (86) is adjacent to the drain of the storage transistor (88) to prevent drain-disturb events. The source-side select transistor (87) is adjacent to the source of the storage transistor (88) to prevent source-disturb events. The select gate (152) of the drain-side select transistor (86), the select gate (143) of the source-side select transistor (87), and the floating gate (147) of the storage transistor (88) are formed on a dielectric layer (123) having a uniform thickness.

Claims

1. A memory array, comprising:

a three-transistor memory cell comprising;

a substrate;

a dielectric layer on the substrate;

a first select gate on a first portion of the dielectric layer;

a floating gate on a second portion of the dielectric layer; and

a second select gate on a third portion of the dielectric layer, wherein a thickness of the dielectric layer between the first select gate and the substrate, between the floating gate and the substrate, and between the second select gate and the substrate is substantially uniform.

2. The memory array of claim 1, wherein the three-transistor memory cell further comprises:

first, second, third, and fourth doped regions extending from a surface of the substrate into the substrate and spaced apart from each other;

wherein the first select gate is between the first doped region and the second doped region;

wherein the floating gate is between the second doped region and the third doped region; and

wherein the second select gate is between the third doped region and the fourth doped region.

3. The memory array of claim 2, wherein the three-transistor memory cell includes a first select transistor, a second select transistor, and a floating gate transistor, wherein the first doped region serves as the drain of the first select transistor, the second doped region serves as both the source region of the first select transistor and as the drain region of floating gate transistor, the third doped region serves as both the source region of the floating gate transistor and as the drain region of the second select transistor, and the fourth doped region serves as the source of the second select transistor.

4. The memory array of claim 1, wherein the thickness of the dielectric layer is less than 90 angstroms.

5. A non-volatile memory cell, comprising:

a substrate having a surface;

a tunnel dielectric layer on the substrate and having a substantially uniform thickness;

a first select transistor having a drain region extending from the surface into the substrate, a source region extending from the surface into the substrate, and a gate on a portion of the tunnel dielectric layer between the source region of the first select transistor and the drain region of the first select transistor;

a floating gate transistor having a drain region extending from the surface into the substrate, a source region, a floating gate on a portion of the tunnel dielectric layer between the source region of the floating gate transistor and the drain region of the floating gate transistor, and a control gate overlying the floating gate, wherein the drain region of the first select transistor and the source region of the floating gate transistor are common; and

a second select transistor having a drain region extending from the surface into the substrate, a source region, a gate on a portion of the tunnel dielectric layer between the source region of the second select transistor and the drain region of the second select transistor, wherein the drain region of the floating gate transistor and the source region of the second select transistor are common.

6. The non-volatile memory cell of claim 5, wherein the substantially uniform thickness of the tunnel dielectric layer is less than approximately 200 angstroms.

7. The non-volatile memory cell of claim 5, wherein the substantially uniform thickness of the tunnel dielectric layer ranges between approximately 40 angstroms and 120 angstroms.

8. The non-volatile memory cell of claim 5, wherein the tunnel dielectric layer is silicon dioxide.

9. The non-volatile memory cell of claim 5, further including an interpoly dielectric separating the floating gate and the control gate of the floating gate transistor.

10. A memory cell, comprising:

a first select transistor having a gate, a drain, and a source;

a storage transistor having a control gate, a floating gate, a drain connected to the source of the first select transistor, and a source; and

a second select transistor having a gate, a drain connected to the source of the storage transistor, and a source, wherein the gate of the first select transistor, the gate of the second select transistor, and the floating gate of the storage transistor are each formed on a dielectric layer having a substantially uniform thickness.

11. The memory cell of claim 10, wherein the first select transistor, the second select transistor, and the storage transistor form a three-transistor memory cell.

12. The memory cell of claim 10, wherein the first and second select transistors are devoid of a floating gate.

13. The memory cell of claim 10, wherein the substantially uniform thickness of the tunnel dielectric layer is less than approximately 90 angstroms.

14. The memory cell of claim 10, wherein the first select transistor is a drain-side select transistor for preventing drain-disturb events.

15. The memory cell of claim 10, wherein the second select transistor is a source-side select transistor for preventing source-disturb events.

16. A memory array, comprising:

a first memory cell having a drain electrode coupled to a bit line of the memory array, a source electrode, a drain-side select gate electrode coupled to a first word line of the memory array, a source-side select gate electrode coupled to a second word line of the memory array, and a control gate electrode coupled to a third word line of the memory array, wherein the first memory cell is a three-transistor memory cell comprising;

a substrate;

a dielectric layer over the substrate;

a first select transistor having a gate, a drain, and a source;

a storage transistor having a control gate, a floating gate, a drain connected to the source of the first select transistor, and a source; and

a second select transistor having a gate, a drain connected to the source of the storage transistor, and a source, wherein a thickness of the dielectric layer between the gate of the first select transistor and the substrate, between the floating gate and the substrate, and between the gate of the second select transistor and the substrate is substantially uniform; and

a second memory cell having a drain electrode coupled to the bit line of the memory array, a source electrode coupled to the source electrode of the first memory cell, a drain-side select gate electrode coupled to a fourth word line of the memory array, a source-side select gate electrode coupled to a fifth word line of the memory array, and a control gate electrode coupled to a sixth word line of the memory array.

17. The memory array of claim 16, wherein the second memory cell is a three-transistor memory cell comprising:

a third select transistor having a gate, a drain, and a source;

a second storage transistor having a control gate, a floating gate, a drain connected to the source of the third select transistor, and a source; and

a fourth select transistor having a gate, a drain connected to the source of the second storage transistor, and a source, wherein the gates of the third and fourth select transistors and the floating gate of the second storage transistor are each formed on the dielectric layer and the thickness of the dielectric layer between the substrate and the gates of the third and fourth select transistors and the substrate and the floating gate of the second storage transistor is substantially uniform.

18. The memory array of claim 16, further comprising:

a third memory cell having a drain electrode coupled to a second bit line of the memory array, a source electrode coupled to the source electrode of the first memory cell, a drain-side select gate electrode coupled to the first word line of the memory array, a source-side select gate electrode coupled to the second word line of the memory array, and a control gate electrode coupled to the third word line of the memory array; and

a fourth memory cell having a drain electrode coupled to the second bit line of the memory array, a source electrode coupled to the source electrode of the first memory cell, a drain-side select gate electrode coupled to the fourth word line of the memory array, a source-side select gate electrode coupled to the fifth word line of the memory array, and a control gate electrode coupled to the sixth word line of the memory array.

19. The memory array of claim 18, wherein the third memory cell is a three-transistor memory cell comprising:

a third select transistor having a gate, a drain, and a source;

a second storage transistor having a control gate, a floating gate, a drain connected to the source of the third select transistor, and a source; and

a fourth select transistor having a gate, a drain connected to the source of the second storage transistor, and a source, wherein the gates of the third and fourth select transistors and the floating gate of the second storage transistor are each formed on the dielectric layer and the thickness of the dielectric layer between the substrate and the gates of the third and fourth select transistors and between the substrate and the floating gate of the second storage transistor is substantially uniform.

20. The memory array of claim 19, wherein the fourth memory cell is a three-transistor memory cell comprising:

a fifth select transistor having a gate, a drain, and a source;

a third storage transistor having a control gate, a floating gate, a drain connected to the source of the fifth select transistor, and a source; and

a sixth select transistor having a gate, a drain connected to the source of the third storage transistor, and a source, wherein the gates of the fifth and sixth select transistors and the floating gate of the third storage transistor are each formed on the dielectric layer and the thickness of the dielectric layer between the substrate and the gates of the fifth and sixth select transistors and between the substrate and the floating gate of the third storage transistor is substantially uniform.