Transistors providing desired threshold voltage and reduced short channel effects with forward body bias

• US 6,232,827 B1
• Filed: 05/13/1998
• Issued: 05/15/2001
• Est. Priority Date: 06/20/1997
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Narendra, Siva G., Keshavarzi, Ali, Borkar, Shekhar Y., De, Vivek K.
• Primary Examiner(s): KIM, JUNG H
• Application Number:
  US09/078,388
• Time in Patent Office: 1,098 Days
• Field of Search: 327/534, 327/535, 327/537, 257/219, 257/391, 257/390, 257/369, 326/34
• US Class Current: 327/537
• CPC Class Codes: H01L 27/0928 comprising both N- and P- wells in the substrate, e.g. twin-tub
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H03K 19/0948 using CMOS or complementary insulated gate field-effect transistors

Abstract

In one embodiment, a semiconductor circuit includes a first group of field effect transistors having a body and parameters including a net channel doping level DL1. The circuit also includes a conductor to provide a first voltage to the body to forward body bias the first group of transistors, the first group of transistors having a forward body bias threshold voltage (VtFBB) when forward body biased, wherein DL1 is at least 25% higher than a net channel doping level in the first group of transistors that would result in a zero body bias threshold voltage equal to VtFBB, with the parameters other than the net channel doping level being unchanged. In another embodiment, the semiconductor circuit includes a first circuit including a first group of field effect transistors having a body. The circuit also includes a first voltage source to provide a first voltage to the body such that the field effect transistors have a forward body bias, the first voltage being at a level leading to the circuit experiencing a reduced rate of soft error failures as compared to when the circuit is not forward biased.

Claims

1. A semiconductor circuit, comprising:

a first group of field effect transistors having a body and parameters including a net channel doping level DL1; and

a conductor to provide a first voltage to the body to forward body bias the first group of transistors, the first group of transistors having a forward body bias threshold voltage (VtFBB) when forward body biased, wherein DL1 is at least 25% higher than a net channel doping level in the first group of transistors that would result in a zero body bias threshold voltage equal to VtFBB, with the parameters other than the net channel doping level being unchanged.

2. The circuit of claim 1, further comprising a second group of field effect transistors having the net channel doping level DL1 and having a non-forward body bias.

3. The circuit of claim 1, wherein the net channel doping includes channel doping and roll off compensation implants.

4. The circuit of claim 2, wherein the first and second group of field effect transistors include roll off compensation implants.

5. The circuit of claim 4, wherein the roll off compensation implants are halo sections.

6. The circuit of claim 4, wherein the roll off compensation implants are angled implants.

7. The circuit of claim 3, wherein the roll off compensation implants are parts of channels of the first and second groups of field effect transistors.

8. The circuit of claim 3, wherein the roll off compensation implants reduce short channel effects.

9. The circuit of claim 1, wherein the first group of field effect transistors includes only p-channel transistors.

10. The circuit of claim 2, wherein the first and second group of field effect transistors each include p-channel field effect transistors (pFET transistors) and n-channel field effect transistors (nFET transistors), and all the pFET transistors are manufactured to have the same parameters and all the nFET transistors are manufactured to have the same parameters.

11. The circuit of claim 1, wherein there may be some unintentional variations in the parameters.

12. The circuit of claim 1, wherein the first group of field effect transistors includes only p-channel field effect transistors and wherein the circuit further comprises a third group of field effect transistors including only n-channel field effect transistors and having a forward body bias threshold voltage which may be a different value than the forward body bias threshold voltage of the first group of field effect transistors when the third group of field effect transistors are forward body biased.

13. The circuit of claim 1, wherein DL1 is at least 50% higher than the net channel doping level in the first group of field effect transistors that would result in a zero body bias threshold voltage equal to VtFBB.

14. The circuit of claim 1, wherein DL1 is at least 75% higher than the net channel doping level in the first group of field effect transistors that would result in a zero body bias threshold voltage equal to VtFBB.

15. The circuit of claim 1, wherein DL1 is at least 100% higher than the net channel doping level in the first group of field effect transistors that would result in a zero body bias threshold voltage equal to VtFBB.

16. A semiconductor circuit, comprising:

a first group of field effect transistors having a first body and parameters including a net channel doping level DL1;

a second group of field effect transistors having a second body and parameters including the net channel doping level DL1;

a first conductor to provide a first voltage to the first body to forward body bias the first group of field effect transistors, the first group of field effect transistors having a forward body bias threshold voltage (VtFBB) when forward body biased, wherein DL1 is higher than a net channel doping level in the first group of field effect transistors that would result in a zero body bias threshold voltage equal to VtFBB, with the parameters other than the net channel doping level being unchanged; and

a second conductor to provide a second voltage to the second body to non-forward body bias the second group of field effect transistors.

17. The circuit of claim 16, wherein DL1 is at least 25% higher than the net channel doping level in the first group of field effect transistors that would result in a zero body bias threshold voltage equal to VtFBB.

18. The circuit of claim 16, wherein DL1 is at least 50% higher than the net channel doping level in the first group of field effect transistors that would result in a zero body bias threshold voltage equal to VtFBB.

19. The circuit of claim 16, wherein DL1 is at least 75% higher than the net channel doping level in the first group of field effect transistors that would result in a zero body bias threshold voltage equal to VtFBB.

20. The circuit of claim 16, wherein DL1 is at least 100% higher than the net channel doping level in the first group of field effect transistors that would result in a zero body bias threshold voltage equal to VtFBB.

21. A method for manufacturing semiconductor circuits in a die, comprising:

fabricating a first group of field effect transistors to have a selected forward body bias threshold voltage; and

fabricating a second group of field effect transistors to have a selected zero body bias threshold voltage, the first and second group of field effect transistors including parameters including a net channel doping level, the net channel doping level being at least 25% higher than that which would provide a zero body bias threshold voltage equal to the forward body bias threshold voltage without a forward body bias with other the parameters being unchanged.

22. The method of claim 21, wherein providing a net channel doping level includes providing channel doping and doping of roll off compensation implants.

23. The method of claim 21, wherein an angled doping is provided before sources and drains are provided.

24. The method of claim 21, wherein providing a net channel doping level includes providing angled implants which extend into the channels of the first and second group of field effect transistors.

25. The method of claim 21, wherein the angled implants reduced short channel effect.

26. The method of claim 21, wherein the first group of field effect transistors are fabricated to have a selected zero body bias threshold voltage.

27. The method of claim 21, wherein the net channel doping level is at least 50% higher than that which would provide a zero body bias threshold voltage equal to the forward body bias threshold voltage without a forward body bias with the other parameters being unchanged.

28. The method of claim 21, wherein the net channel doping level is at least 75% higher than that which would provide a zero body bias threshold voltage equal to the forward body bias threshold voltage without a forward body bias with the other parameters being unchanged.

29. The method of claim 21, wherein the net channel doping level is at least 100% higher than that which would provide a zero body bias threshold voltage equal to the forward body bias threshold voltage without a forward body bias with the other parameters being unchanged.

30. A method for manufacturing semiconductor circuits in a die, comprising:

selecting a target leakage current upper limit and a target switching speed lower limit;

fabricating a conductor to provide a forward body bias voltage; and

fabricating first and second groups of field effect transistors to have parameters including threshold voltages to have leakage be lower than the target leakage current upper limit, the first group of field effect transistors receiving the forward body bias voltage, the forward body bias voltage being such that the switching speed of the first group of field effect transistors is above the target switching speed lower limit, and wherein the first and second group of field effect transistors have parameters including a channel doping level that is higher than that which would provide leakage equal to the target leakage current upper limit at zero body bias with the other parameters being unchanged, wherein the net doping level is at least 25% higher than that which would provide leakage equal to the target leakage current upper limit at zero body bias with the other parameters being unchanged.

31. The method of claim 30, wherein the second group of field effect transistors is also forward body biased.