Clocking technique for reducing sampling noise in an analog-to-digital converter

• US 6,232,905 B1
• Filed: 03/08/1999
• Issued: 05/15/2001
• Est. Priority Date: 03/08/1999
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Guardian Corp. (Broadcom, Inc.)
• Inventors: Smith, Malcolm H., Mo, Jiancheng
• Primary Examiner(s): Williams, Howard L.
• Assistant Examiner(s): Jeanglaude, Jean Bruner
• Application Number:
  US09/263,952
• Time in Patent Office: 799 Days
• Field of Search: 341/155, 341/118, 341/115, 341/126, 358/149
• US Class Current: 341/155
• CPC Class Codes: H03M 1/0836 of phase error, e.g. jitter
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence

Abstract

A method and apparatus are disclosed for improving the operation of an analog-to-digital converter (“ADC”). A separate “clean” oscillator clock is to be used in combination with a “noisy” ADC clock being regulated by a phase-locked-loop (PLL) circuit. The “noisy” ADC clock drives the digital control logic and also turns on the sample signal for the purpose of sampling. The second clock, which has a substantially fixed (i.e., “clean”) frequency is used to generate a short pulse, the leading edge of which turns off the sample signal, thereby providing an improved sampling process with greater resolution. The interaction of the two clocks is controlled with digital logic circuitry.

Claims

1. An apparatus for use with an analog-to-digital converter (ADC), the apparatus comprising:

at least one logic signal passing device, said device comprising a plurality of output control inputs and at least one output;

a first signal source for producing at least a first input signal driven by a first clock source, said first signal source being coupled to at least a first one of said plurality of inputs of said logic signal passing device, said at least a first input signal enabling said ADC to begin a sampling process; and

a second signal source for producing at least a first portion of a second input signal driven by a second clock source, said second signal source being coupled to at least a second one of said plurality of inputs of said logic signal passing device, said at least a first portion of said second input signal disabling said ADC'"'"'s ability to sample.

2. The apparatus as in claim 1, wherein one of said first, said second and a third signal source produces at least a second portion of said second input signal, one of said first, said second, and said third signal source being coupled to said at least a second one of said plurality of inputs of said logic signal passing device, one of said first, said second, and said third signal source also driving said second portion of said second input signal by one of said first, said second, and a third clock source.

3. The apparatus as in claim 1 further comprising:

a non-overlap generator, an input of said generator being coupled to said at least one output of said at least one logic signal passing device; and

a sample and hold circuit, an input of said sample and hold circuit being coupled to an output of said non-overlap generator.

4. The apparatus as in claim 1, wherein said at least one logic signal passing device further comprises a flip-flop.

5. The apparatus as in claim 4, wherein said flip-flop further comprises an RS latch.

6. The apparatus as in claim 5, wherein said at least a first input further comprises a set input of said RS latch.

7. The apparatus as in claim 1, wherein said first source further comprises at least one stage of a logic counter.

8. The apparatus as in claim 7, wherein a clock input of each stage of said logic counter is coupled to said first clock source.

9. The apparatus as in claim 8, wherein said logic counter further comprises a rotating ones counter.

10. The apparatus as in claim 9, wherein said rotating ones counter further comprises a plurality of cascade connected D type flip-flops.

11. The apparatus as in claim 1, wherein said first clock source is of a greater frequency than said second clock source.

12. The apparatus as in claim 11, wherein a frequency of said first clock source is at least n+1 times greater than a frequency of said second clock source, where n is a number of bits of resolution.

13. The apparatus as in claim 1, wherein said first clock source is regulated with a phase locked loop circuit (PLL).

14. The apparatus as in claim 13, wherein said first clock source is a divided down version of a voltage controlled oscillator.

15. The apparatus as in claim 13, wherein a reference clock of said PLL is a divided down version of a voltage controlled oscillator.

16. The apparatus as in claim 15, wherein said reference clock is a divided down version of said first clock source.

17. The apparatus as in claim 1, wherein said first clock source further comprises a divided down version of a high frequency external clock.

18. The apparatus as in claim 1, wherein said second signal source produces a rising edge of said second input signal.

19. The apparatus as in claim 2, wherein one of said first, said second, and said third signal source produces a falling edge of said second input signal.

20. The apparatus as in claim 2, wherein said second signal source further comprises a logic circuit, said logic circuit further comprising:

a plurality of clock sources;

a pulse generator circuit for driving said at least a first portion of said second input signal, said pulse generator circuit being coupled to at least one of said plurality of clock sources; and

a delay circuit for driving said at least a second portion of said second input signal, said delay circuit being coupled to at least one of said plurality of clock sources, and said delay circuit also being coupled to said pulse generator circuit.

21. The apparatus as in claim 20, wherein said plurality of clock sources further comprise:

an oscillator clock; and

a divided down version of a voltage controlled oscillator clock.

22. The apparatus as in claim 21 further comprising a divided down version of an external high frequency clock.

23. The apparatus as in claim 20 further comprising at least one multiplexer (MUX), said MUX further comprising at least two inputs and at least one output, said at least two inputs being respectively coupled to at least a first two of said plurality of clock sources, said at least one output being coupled to said pulse generator circuit.

24. The apparatus as in claim 20, wherein said delay circuit further comprises at least one flip-flop, said at least one flip-flop serving to delay an occurrence of said second portion of said second input signal.

25. The apparatus as in claim 20, wherein said pulse generator circuit further comprises:

a first inverter, an output of said first inverter being coupled to said at least a second input of said at least one logic signal passing device;

a NAND gate, an output of which is coupled to an input of said first inverter, a first input of which is coupled to said delay circuit segment;

a first NOR gate, an output of which is coupled to a second input of said NAND gate, a first input of which is coupled to an output of said MUX;

a second NOR gate, an output of which is coupled to a second input of said first NOR gate;

at least one D flip-flop, an output of which is coupled to an input of said second NOR gate, an input of which is coupled to an ADC enable signal, a clock input of said at least one D flip-flop being coupled to a second inverter, and wherein

an input of said second inverter is coupled to an oscillator clock; and

a third inverter, an output of which is coupled to an input of said second NOR gate, an input of which is coupled to an oscillator clock bypass signal.

26. The apparatus as in claim 20, wherein said delay circuit further comprises:

a first inverter, an output of said first inverter being coupled to a first input of a first NAND gate, an input of said first inverter being coupled to an output of a first flip-flop;

an AND gate, an output of which is coupled to a clock input of at least said first flip-flop, an input of which is coupled to a reset input of at least said first flip-flop; and

a NAND gate, an output of which is coupled to a clock input of at least a second flip-flop, an input of which is coupled to an input of said AND gate.

27. An integrated circuit (IC) comprising:

an analog to digital converter (ADC) including a sample and hold circuit; and

an apparatus for use with said analog-to-digital converter, said apparatus further comprising;

at least one logic signal passing device, said device comprising a plurality of output control inputs and at least one output;

a first signal source for producing at least a first input signal driven by a first clock source, said first signal source being coupled to at least a first one of said plurality of inputs of said logic signal passing device, said at least a first input signal enabling said ADC to begin a sampling process; and

a second signal source for producing at least a first portion of a second input signal driven by a second clock source, said second signal source being coupled to at least a second one of said plurality of inputs of said logic signal passing device, said at least a first portion of said second input signal disabling said ADC'"'"'s ability to sample.

28. The IC of claim 27, wherein one of said first, said second and a third signal source produces at least a second portion of said second input signal, one of said first, said second, and said third signal source being coupled to said at least a second one of said plurality of inputs of said logic signal passing device, one of said first, said second, and said third signal source also driving said second portion of said second input signal by one of said first, said second, and a third clock source.

29. The IC of claim 27, said apparatus further comprising:

a non-overlap generator, an input of said generator being coupled to said at least one output of said at least one logic signal passing device; and

a sample and hold circuit, an input of said sample and hold circuit being coupled to an output of said non-overlap generator.

30. The IC of claim 27, wherein said at least one logic signal passing device further comprises a flip-flop.

31. The IC of claim 30, wherein said flip-flop further comprises an RS latch.

32. The IC of claim 31, wherein said at least a first input further comprises a set input of said RS latch.

33. The IC of claim 27, wherein said first source further comprises at least one stage of a logic counter.

34. The IC of claim 33, wherein a clock input of each stage of said logic counter is coupled to said first clock source.

35. The IC of claim 34, wherein said logic counter further comprises a rotating ones counter.

36. The IC of claim 35, wherein said rotating ones counter further comprises a plurality of cascade connected D type flip-flops.

37. The IC of claim 27, wherein said first clock source is of a greater frequency than said second clock source.

38. The IC of claim 37, wherein a frequency of said first clock source is at least n+1 times greater than a frequency of said second clock source, where n is a number of bits of resolution.

39. The IC of claim 27, wherein said first clock source is regulated with a phase locked loop circuit (PLL).

40. The IC of claim 39, wherein said first clock source is a divided down version of a voltage controlled oscillator.

41. The IC of claim 39, wherein a reference clock of said PLL is a divided down version a voltage controlled oscillator.

42. The IC of claim 41, wherein said reference clock is a divided down version of said first clock source.

43. The IC of claim 27, wherein said first clock source further comprises a divided down version of a high frequency external clock.

44. The IC of claim 27, wherein said second signal source is capable of producing a rising edge of said second input signal.

45. The IC of claim 28, wherein one of said first, said second, and said third signal source produces a falling edge of said second input signal.

46. The IC of claim 28, wherein said second signal source further comprises a logic circuit, said logic circuit further comprising:

a plurality of clock sources;

a pulse generator circuit for driving said at least a first portion of said second input signal, said pulse generator circuit being coupled to at least one of said plurality of clock sources; and

a delay circuit for driving said at least a second portion of said second input signal, said delay circuit being coupled to at least one of said plurality of clock sources, and said delay circuit also being coupled to said pulse generator circuit.

47. The IC of claim 46, wherein said plurality of clock sources further comprise:

an oscillator clock; and

a divided down version of a voltage controlled oscillator clock.

48. The IC of claim 47 further comprising a divided down version of an external high frequency clock.

49. The IC of claim 46 further comprising at least one multiplexer (MUX), said MUX further comprising at least two inputs and at least one output, said at least two inputs being respectively coupled to at least a first two of said plurality of clock sources, said at least one output being coupled to said pulse generator circuit.

50. The IC of claim 46, wherein said delay circuit further comprises at least one flip-flop, said at least one flip-flop serving to delay an occurrence of said second portion of said second input signal.

51. The IC of claim 46, wherein said pulse generation circuit further comprises:

a first inverter, an output of said first inverter being coupled to said at least a second input of said at least one logic signal passing device;

a NAND gate, an output of which is coupled to an input of said first inverter, a first input of which is coupled to said delay circuit segment;

a first NOR gate, an output of which is coupled to a second input of said NAND gate, a first input of which is coupled to an output of said MUX;

a second NOR gate, an output of which is coupled to a second input of said first NOR gate;

at least one D flip-flop, an output of which is coupled to an input of said second NOR gate, an input of which is coupled to an ADC enable signal, a clock input of said at least one D flip-flop being coupled to a second inverter, and wherein

an input of said second inverter is coupled to an oscillator clock; and

a third inverter, an output of which is coupled to an input of said second NOR gate, an input of which is coupled to an oscillator clock bypass signal.

52. The IC of claim 46, wherein said delay circuit segment further comprises:

a first inverter, an output of said first inverter being coupled to a first input of a first NAND gate, an input of said first inverter being coupled to an output of a first flip-flop;

an AND gate, an output of which is coupled to a clock input of at least said first flip-flop, an input of which is coupled to a reset input of at least said first flip-flop; and

a NAND gate, an output of which is coupled to a clock input of at least a second flip-flop, an input of which is coupled to an input of said AND gate.

53. A method of improving performance of an analog-to-digital converter (ADC), the method comprising:

generating a first signal, said first signal being derived from a first source and said first signal being driven by a first clock source;

receiving said first signal at at least a first input of a logic signal passing device so as to cause a first condition of said logic signal passing device;

starting a sampling process as a result of said first condition;

generating at least a first portion of a second signal, said at least a first portion being derived from a second source and said at least a first portion of said second signal being driven by a second clock source;

receiving said at least a first portion of said second signal at at least a second input of said logic signal passing device so as to cause a second condition of said logic signal passing device; and

ending said sampling process as a result of said second condition.

54. The method as in claim 53 further comprising:

starting an analog-to-digital (A/D) conversion process;

generating at least a second portion of said second signal, said at least a second portion being derived from one of either said first, said second, or a third source and said at least a second portion being driven by one of a plurality of clock sources; and

receiving said at least a second portion of said second signal at said second input of said logic signal passing device.

55. The method as in claim 53, wherein said act of generating a first signal further comprises generating said first signal from at least one stage of a counter circuit.

56. The method as in claim 53, wherein said act of generating a first signal further comprises regulating said first clock source with a phase locked loop circuit.

57. The method as in claim 56, wherein said act of regulating further comprises dividing down a voltage controlled oscillator clock frequency.

58. The method as in claim 53, wherein said act of generating a first signal further comprises dividing down an external clock frequency.

59. The method as in claim 53, wherein said act of receiving said at least a first portion further comprises receiving a rising edge of said second signal.

60. The method as in claim 53, wherein said act of receiving said at least a first portion further comprises causing an RS latch to set.

61. The method as in claim 53, wherein said act of generating at least a first portion of a second signal further comprises selecting one of at least an oscillator clock source and an external clock source.

62. The method as in claim 53, wherein said act of generating at least a first portion of a second signal further comprises enabling said act of generating only if said ADC is enabled.

63. The method as in claim 53, wherein said act of receiving said at least a first portion of said second signal further comprises causing an RS latch to reset.

64. The method as in claim 54, wherein said act of starting an A/D conversion process further comprises starting a successive approximation process.

65. The method as in claim 54, wherein said act of starting an A/D conversion process further comprises starting an iterative algorithmic conversion process.

66. The method as in claim 54, wherein said act of starting an A/D conversion process further comprises starting a sub-ranging conversion process.

67. The method as in claim 54, wherein said act of starting an A/D conversion process further comprises starting an integrating conversion process.

68. The method as in claim 54, wherein said act of generating at least a second portion further comprises generating a falling edge of said second signal.

69. The method as in claim 54, wherein said act of generating at least a second portion further comprises delaying said second portion until said first condition has occurred.

70. The method as in claim 54, wherein said act of generating at least a second portion further comprises generating said second portion before said sampling process in completed.

71. The method as in claim 54, wherein said act of generating at least a second portion further comprises selecting one of at least an oscillator clock source, an external clock source, or a divided down version of a voltage controlled oscillator clock source to drive said at least a second portion of said second signal.

72. The method as in claim 54, wherein said act of receiving said at least a second portion of said second signal further comprises receiving said second portion at a reset input of an RS latch.