Wafer level burn-in of memory integrated circuits

• US 6,233,185 B1
• Filed: 02/25/1999
• Issued: 05/15/2001
• Est. Priority Date: 08/21/1997
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Farnworth, Warren M., Cloud, Eugene H., Nevill, Leland R., Waller, William K., Beffa, Ray
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US09/257,403
• Time in Patent Office: 810 Days
• Field of Search: 365/96, 365/189.01, 365/230.01, 365/201, 365/218
• US Class Current: 365/201
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 2029/1202 Word line control
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing

Abstract

A memory self-stress mode capable of use during wafer burn-in such as for dynamic random access memory (DRAM) integrated circuits. A burn-in power supply voltage and ground voltage delivered to a common node of a plurality of memory cell storage capacitors and to an equilibrate node coupled to bit lines. An all row high test cycles word lines between a binary low logic level and a binary high logic level, thereby stressing the dielectric of the memory cell storage capacitors by imposing stress voltages of differing polarity. A half row high test cycles alternate word lines of a word line sequence thereby stressing undesired short circuit connections between adjacent word lines.

Claims

1. A system for stress testing a memory integrated circuit die, the memory integrated circuit die including a plurality of memory cells, a plurality of bit lines, a sequence of word lines, and a common node, with each memory cell coupled to one of the bit lines, one of the word lines and the common node, the system comprising:

a voltage source having a polarity and a burn-in voltage differential, the voltage source coupled across the common node and a corresponding bit line for a memory cell,

wherein the voltage source supplies a burn-in voltage to alternate word lines of the sequence of word lines.

2. The system of claim 1, wherein the polarity is reversed one or more times.

3. The system of claim 1, wherein the voltage source includes a burn-in power supply node on the memory integrated circuit die, the burn-in power supply node being independent of a normal operation voltage source used during normal operation of the memory integrated circuit die.

4. The system of claim 1, wherein the voltage source superimposes a clock signal on the burn-in voltage differential.

5. A system for stress testing a memory integrated circuit die, the memory integrated circuit die including a plurality of memory cells, a plurality of bit lines and a sequence of word lines which includes a pair of adjacent word lines, the pair of adjacent word lines including a first word line and a second word line, the plurality of memory cells having a common node and a storage node, the system comprising:

a voltage source having a polarity and a burn-in voltage differential, the voltage source coupled across the first word line and the second word line,

wherein the voltage source is operable for reversing the polarity one or more times.

6. The system of claim 5, wherein the memory integrated circuit die is isolated from the voltage source upon determining insulation between the pair of adjacent word lines fails.

7. The system of claim 5, wherein the voltage source is capable of being coupled across the common node and the storage node of one of the memory cells and across one bit line and one word line.

8. The system of claim 7, wherein the memory integrated circuit die is isolated from the voltage source upon determining insulation between the common node and the storage node fails.

9. The system of claim 7, wherein the memory integrated circuit die is isolated from the voltage source upon determining insulation between the one bit line and the one word line fails.

10. The system of claim 5, wherein the voltage source includes a burn-in power supply node on the memory integrated circuit die, the burn-in power supply node being independent of a normal operation voltage source used during normal operation of the memory integrated circuit die.

11. The system of claim 5, wherein the voltage source superimposes a clock signal on the burn-in voltage differential.

16. The system of claim 11, wherein the polarity is reversed one or more times.

17. The system of claim 11, wherein the voltage source includes a burn-in power supply node on the memory integrated circuit die, the burn-in power supply node being independent of a normal operation voltage source used during normal operation of the memory integrated circuit die.

18. The system of claim 11, wherein the voltage source superimposes a clock signal on the burn-in voltage differential.

12. A system for stressing insulation in a memory integrated circuit die, the memory integrated circuit die including a plurality of memory cells, a plurality of bit lines and a sequence of word lines which includes a pair of adjacent word lines, the plurality of memory cells having a common node and a storage node, the system comprising:

a voltage source having a polarity and a burn-in voltage differential, the voltage source being coupled across the pair of adjacent word lines, across the common node and the storage node of one of the memory cells, and across one bit line and one word line,

wherein the voltage source is operable for reversing the polarity one or more times.

13. The system of claim 12, wherein the voltage source includes a burn-in power supply node on the memory integrated circuit die, the burn-in power supply node being independent of a normal operation voltage source used during normal operation of the memory integrated circuit die.

14. The system of claim 12, wherein the voltage source superimposes a clock signal on the burn-in voltage differential.

15. A system for stress testing a memory integrated circuit die, the system comprising:

a memory integrated circuit die including;

a plurality of memory cells;

a plurality of bit lines;

a sequence of word lines; and

a common node,

wherein each memory cell is coupled to one of the plurality of bit lines, one of the sequence of word lines and the common node; and

a voltage source coupled across the common node and a corresponding bit line for a memory cell of the memory integrated circuit die, the voltage source having a polarity and a burn-in voltage differential,

wherein the voltage source supplies a burn-in voltage to alternate word lines of the sequence of word lines.

19. A system for stress testing a memory integrated circuit die, the system comprising:

a memory integrated circuit die including;

a plurality of memory cells having a common node and a storage node;

a plurality of bit lines; and

a sequence of word lines having a pair of adjacent word lines such that the pair of adjacent word lines include a first word line and a second word line,

wherein each memory cell is coupled to one of the plurality of bit lines and one of the sequence of word lines; and

a voltage source having a polarity and a burn-in voltage differential, the voltage source coupled across the first word line and the second word line,

wherein the voltage source is operable for reversing the polarity one or more times.

20. The system of claim 19, wherein the memory integrated circuit die is isolated from the voltage source upon determining insulation between the pair of adjacent word lines fails.

21. The system of claim 19, wherein the voltage source is capable of being coupled across the common node and the storage node of one of the memory cells and across one bit line and one word line.

22. The system of claim 21, wherein the memory integrated circuit die is isolated from the voltage source upon determining insulation between the common node and the storage node fails.

23. The system of claim 21, wherein the memory integrated circuit die is isolated from the voltage source upon determining insulation between the one bit line and the one word line fails.

24. The system of claim 19, wherein the voltage source includes a burn-in power supply node on the memory integrated circuit die, the burn-in power supply node being independent of a normal operation voltage source used during normal operation of the memory integrated circuit die.

25. The system of claim 19, wherein the voltage source superimposes a clock signal on the burn-in voltage differential.

26. A system for stressing insulation in a memory integrated circuit die, the system comprising:

a memory integrated circuit die including;

a plurality of memory cells having a common node and a storage node;

a plurality of bit lines operatively coupled to the plurality of memory cells; and

a sequence of word lines operatively coupled to the plurality of memory cells and the plurality of bit lines, the sequence of word line having a pair of adjacent word lines.

wherein each memory cell is coupled to one of the plurality of bit lines and one of the sequence of word lines; and

a voltage source having a polarity and a burn-in voltage differential, the voltage source being coupled across the pair of adjacent word lines, across the common node and the storage node of one of the memory cells, and across one bit line and one word line,

wherein the voltage source is operable for reversing the polarity one or more times.

27. The system of claim 26, wherein the voltage source includes a burn-in power supply node on the memory integrated circuit die, the burn-in power supply node being independent of a normal operation voltage source used during normal operation of the memory integrated circuit die.

28. The system of claim 26, wherein the voltage source superimposes a clock signal on the burn-in voltage differential.