Method of anti-fuse repair

• US 6,233,194 B1
• Filed: 04/27/2000
• Issued: 05/15/2001
• Est. Priority Date: 08/20/1996
• Status: Expired due to Term

• Current Assignee: Conversant Intellectual Property Management Inc (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: Micron Technology, Inc.
• Inventors: Marr, Kenneth W., Batra, Shubneesh
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US09/560,498
• Time in Patent Office: 383 Days
• Field of Search: 365/225.7, 257/530, 257/410, 438/600
• US Class Current: 365/225.7
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An integrated circuit anti-fuse is described which is fabricated as a capacitor using a layer of oxide. The two plates of the anti-fuse are coupled to appropriate voltage levels to rupture the oxide and form a conductive short between the plates. One of the plates is formed as a diffused well which is coupled to an external voltage during programming. The well is biased to an internal voltage during normal operation of the circuit incorporating the anti-fuse.

Claims

1. An anti-fuse comprising:

a well of a first conductivity type in a substrate of a second conductivity type;

a diffusion region of the first conductivity type in the well; and

an insulator between the well and a conductive plate.

2. The anti-fuse of claim 1 wherein the conductive plate comprises polysilicon.

3. The anti-fuse of claim 1 wherein the conductive plate comprises polysilicon of the first conductivity type.

4. The anti-fuse of claim 1 wherein the diffusion region comprises a well tie diffusion region having a higher dopant concentration than the well.

5. The anti-fuse of claim 1 wherein:

the insulator comprises a layer of oxide; and

the substrate comprises silicon.

6. The anti-fuse of claim 1 wherein:

the substrate comprises a p-type silicon substrate;

the well comprises an n-type well in the substrate;

the diffusion region comprises an n+-type well tie diffusion region;

the insulator comprises a layer of oxide; and

the conductive plate comprises a layer of n-type polysilicon.

7. The anti-fuse of claim 1 wherein:

the substrate comprises an n-type silicon substrate;

the well comprises a p-type well in the substrate;

the diffusion region comprises a p+-type well tie diffusion region;

the insulator comprises a layer of oxide; and

the conductive plate comprises a layer of p-type polysilicon.

8. An anti-fuse comprising:

a well of a first conductivity type in a substrate of a second conductivity type;

a well tie diffusion region of the first conductivity type in the well, the well tie diffusion region having a higher dopant concentration than the well; and

an insulator between the well and a conductive plate.

9. The anti-fuse of claim 8 wherein:

the substrate comprises a p-type silicon substrate;

the well comprises an n-type well in the substrate;

the well tie diffusion region comprises an n+-type well tie diffusion region;

the insulator comprises a layer of oxide; and

the conductive plate comprises a layer of n-type polysilicon.

10. The anti-fuse of claim 8 wherein:

the substrate comprises an n-type silicon substrate;

the well comprises a p-type well in the substrate;

the well tie diffusion region comprises a p+-type well tie diffusion region;

the insulator comprises a layer of oxide; and

the conductive plate comprises a layer of p-type polysilicon.

11. A method comprising:

coupling a first programming voltage to a conductive plate of an anti-fuse; and

coupling a second programming voltage to a well of a first conductivity type of the anti-fuse to create a current path through an insulator between the conductive plate and the well to program the anti-fuse.

12. The method of claim 11 wherein coupling a second programming voltage comprises coupling a second programming voltage to a diffusion region of the first conductivity type in a well of the first conductivity type in a substrate of a second conductivity type in the anti-fuse to create a current path through an insulator between the conductive plate and the well to program the anti-fuse.

13. The method of claim 11 wherein coupling a first programming voltage comprises coupling a first programming voltage to a layer of polysilicon in an anti-fuse.

14. The method of claim 11 wherein:

coupling a first programming voltage comprises coupling a first programming voltage to a layer of n-type polysilicon in an anti-fuse; and

coupling a second programming voltage comprises coupling a second programming voltage to an n+-type diffusion region in an n-type well in a p-type substrate in the anti-fuse to create a current path through an insulating layer of oxide between the layer of n-type polysilicon and the n-type well to program the anti-fuse.

15. The method of claim 11 wherein:

coupling a first programming voltage comprises coupling a first programming voltage to a layer of p-type polysilicon in an anti-fuse; and

coupling a second programming voltage comprises coupling a second programming voltage to a p+-type diffusion region in a p-type well in an n-type substrate in the anti-fuse to create a current path through an insulating layer of oxide between the layer of p-type polysilicon and the p-type well to program the anti-fuse.

16. A method comprising:

coupling a first programming voltage to a conductive plate of an anti-fuse; and

coupling a second programming voltage to a diffusion region of a first conductivity type in a well of the first conductivity type in a substrate of a second conductivity type in the anti-fuse to create a current path through an insulator between the conductive plate and the well to program the anti-fuse.

17. The method of claim 16 wherein:

coupling a first programming voltage comprises coupling a first programming voltage to a layer of n-type polysilicon in an anti-fuse; and

coupling a second programming voltage comprises coupling a second programming voltage to an n+-type diffusion region in an n-type well in a p-type substrate in the anti-fuse to create a current path through an insulating layer of oxide between the layer of n-type polysilicon and the n-type well to program the anti-fuse.

18. The method of claim 16 wherein:

coupling a first programming voltage comprises coupling a first programming voltage to a layer of p-type polysilicon in an anti-fuse; and

coupling a second programming voltage comprises coupling a second programming voltage to a p+-type diffusion region in a p-type well in an n-type substrate in the anti-fuse to create a current path through an insulating layer of oxide between the layer of p-type polysilicon and the p-type well to program the anti-fuse.

19. An integrated circuit comprising:

a first circuit;

a second circuit; and

a plurality of anti-fuses coupled between the first circuit and the second circuit, each anti-fuse comprising;

a well of a first conductivity type in a substrate of a second conductivity type;

a diffusion region of the first conductivity type in the well; and

an insulator between the well and a conductive plate.

20. The integrated circuit of claim 19 wherein the conductive plate comprises polysilicon.

21. The integrated circuit of claim 19 wherein the conductive plate comprises polysilicon of the first conductivity type.

22. The integrated circuit of claim 19 wherein the diffusion region comprises a well tie diffusion region having a higher dopant concentration than the well.

23. The integrated circuit of claim 19 wherein:

the insulator comprises a layer of oxide; and

the substrate comprises silicon.

24. The integrated circuit of claim 19 wherein:

the substrate comprises a p-type silicon substrate;

the well comprises an n-type well in the substrate;

the diffusion region comprises an n+-type well tie diffusion region;

the insulator comprises a layer of oxide; and

the conductive plate comprises a layer of n-type polysilicon.

25. The integrated circuit of claim 19 wherein:

the substrate comprises an n-type silicon substrate;

the well comprises a p-type well in the substrate;

the diffusion region comprises a p+-type well tie diffusion region;

the insulator comprises a layer of oxide; and

the conductive plate comprises a layer of p-type polysilicon.

26. The integrated circuit of claim 19 wherein:

the first circuit comprises a programming logic circuit; and

the second circuit comprises an external connection and a bias network.

27. The integrated circuit of claim 19 wherein the integrated circuit comprises a memory device and further comprises a memory array, and address decoder, and input/output paths.

28. An integrated circuit comprising:

a first circuit;

a second circuit; and

a plurality of anti-fuses coupled between the first circuit and the second circuit, each anti-fuse comprising;

a well of a first conductivity type in a substrate of a second conductivity type;

a well tie diffusion region of the first conductivity type in the well, the well tie diffusion region having a higher dopant concentration than the well; and

an insulator between the well and a conductive plate.

29. The integrated circuit of claim 28 wherein:

the substrate comprises a p-type silicon substrate;

the well comprises an n-type well in the substrate;

the well tie diffusion region comprises an n+-type well tie diffusion region;

the insulator comprises a layer of oxide;

the conductive plate comprises a layer of n-type polysilicon;

the first circuit comprises a programming logic circuit;

the second circuit comprises an external connection and a bias network; and

the integrated circuit comprises a memory device and further comprises a memory array, an address decoder, and input/output paths.

30. The integrated circuit of claim 28 wherein:

the substrate comprises an n-type silicon substrate;

the well comprises a p-type well in the substrate;

the well tie diffusion region comprises a p+-type well tie diffusion region;

the insulator comprises a layer of oxide;

the conductive plate comprises a layer of p-type polysilicon;

the first circuit comprises a programming logic circuit;

the second circuit comprises an external connection and a bias network; and

the integrated circuit comprises a memory device and further comprises a memory array, an address decoder, and input/output paths.

31. A method of operating an integrated circuit comprising:

selecting an anti-fuse from a plurality of anti-fuses coupled between a first circuit and a second circuit in the integrated circuit;

coupling a first programming voltage to a conductive plate of the selected anti-fuse; and

coupling a second programming voltage to a well of a first conductivity type of the selected anti-fuse to create a current path through an insulator between the conductive plate and the well to program the selected anti-fuse.

32. The method of claim 31 wherein coupling a second programming voltage comprises coupling a second programming voltage to a diffusion region of a first conductivity type in a well of the first conductivity type in a substrate of a second conductivity type in the selected anti-fuse to create a current path through an insulator between the conductive plate and the well to program the selected anti-fuse.

33. The method of claim 31 wherein coupling a first programming voltage comprises coupling a first programming voltage to a layer of polysilicon in the selected anti-fuse.

34. The method of claim 31 wherein:

coupling a first programming voltage comprises coupling a first programming voltage to a layer of n-type polysilicon in the selected anti-fuse; and

coupling a second programming voltage comprises coupling a second programming voltage to an n+-type diffusion region in an n-type well in a p-type silicon substrate in the selected anti-fuse to create a current path through an insulating layer of oxide between the layer of n-type polysilicon and the n-type well to program the selected anti-fuse.

35. The method of claim 31 wherein:

coupling a first programming voltage comprises coupling a first programming voltage to a layer of p-type polysilicon in the selected anti-fuse; and

coupling a second programming voltage comprises coupling a second programming voltage to a p+-type diffusion region in a p-type well in an n-type silicon substrate in the selected anti-fuse to create a current path through an insulating layer of oxide between the layer of p-type polysilicon and the p-type well to program the selected anti-fuse.

36. The method of claim 31 wherein:

selecting an anti-fuse comprises selecting an anti-fuse from a plurality of anti-fuses coupled between a programming logic circuit and a connection external to the integrated circuit coupled to a bias network in the integrated circuit;

coupling a first programming voltage comprises coupling a first programming voltage from the programming logic circuit to a conductive plate of the selected anti-fuse; and

coupling a second programming voltage comprises coupling a second programming voltage to the connection external to the integrated circuit that is coupled to a well of a first conductivity type of the selected anti-fuse to create a current path through an insulator between the conductive plate and the well to program the selected anti-fuse.

37. A method of operating an integrated circuit comprising:

selecting an anti-fuse from a plurality of anti-fuses coupled between a first circuit and a second circuit in the integrated circuit;

coupling a first programming voltage to a conductive plate of the selected anti-fuse; and

coupling a second programming voltage to a diffusion region of a first conductivity type in a well of the first conductivity type in a substrate of a second conductivity type in the selected anti-fuse to create a current path through an insulator between the conductive plate and the well to program the selected anti-fuse.

38. The method of claim 37 wherein:

selecting an anti-fuse comprises selecting an anti-fuse from a plurality of anti-fuses coupled between a programming logic circuit and a connection external to the integrated circuit coupled to a bias network in the integrated circuit;

coupling a first programming voltage comprises coupling a first programming voltage from the programming logic circuit to a layer of n-type polysilicon in the selected anti-fuse; and

coupling a second programming voltage comprises coupling a second programming voltage to the connection external to the integrated circuit that is coupled to an n+-type diffusion region in an n-type well in a p-type silicon substrate in the selected anti-fuse to create a current path through an insulating layer of oxide between the layer of n-type polysilicon and the n-type well to program the selected anti-fuse.

39. The method of claim 37 wherein:

selecting an anti-fuse comprises selecting an anti-fuse from a plurality of anti-fuses coupled between a programming logic circuit and a connection external to the integrated circuit coupled to a bias network in the integrated circuit;

coupling a first programming voltage comprises coupling a first programming voltage from the programming logic circuit to a layer of p-type polysilicon in the selected anti-fuse;

coupling a second programming voltage comprises coupling a second programming voltage to the connection external to the integrated circuit that is coupled to a p+-type diffusion region in a p-type well in an n-type silicon substrate in the selected anti-fuse to create a current path through an insulating layer of oxide between the layer of p-type polysilicon and the p-type well to program the selected anti-fuse.

40. An integrated circuit comprising:

a circuit;

a plurality of anti-fuses, each anti-fuse having a first conductive plate coupled to the circuit to receive a first programming voltage, and a second conductive plate; and

a connection external to the integrated circuit coupled to the second conductive plate of each anti-fuse to receive a second programming voltage to be coupled to the second conductive plate of each anti-fuse.

41. The integrated circuit of claim 40 wherein the circuit comprises a programming logic circuit.

42. The integrated circuit of claim 40, further comprising a bias network coupled to the second conductive plate of each anti-fuse.

43. The integrated circuit of claim 40 wherein:

the second conductive plate comprises a well of a first conductivity type in a substrate of a second conductivity type;

the first conductive plate is separated from the well be an insulator; and

the connection external to the integrated circuit comprises a pin of the integrated circuit.

44. A method of operating an integrated circuit comprising:

selecting an anti-fuse from a plurality of anti-fuses coupled between a circuit in the integrated circuit and a connection external to the integrated circuit;

coupling a first programming voltage to a first conductive plate of the selected anti-fuse from the circuit; and

coupling a second programming voltage to a second conductive plate in the selected anti-fuse from the connection external to the integrated circuit to create a current path through an insulator between the first conductive plate and the second conductive plate to program the selected anti-fuse.

45. The method of claim 44 wherein coupling a first programming voltage comprises coupling a first programming voltage to a first conductive plate of the selected anti-fuse from a programming logic circuit.

46. The method of claim 44, further comprising biasing the second conductive plate of each anti-fuse with a bias network.

47. The method of claim 44 wherein coupling a second programming voltage comprises coupling a second programming voltage to a well of a first conductivity type in a substrate of a second conductivity type in the selected anti-fuse from a pin of the integrated circuit to create a current path through an insulator between the first conductive plate and the well to program the selected anti-fuse.