Network switch with shared memory system
First Claim
1. A network switch for enabling communication among a plurality of network devices, comprising:
- a plurality of network ports that receive and transmit data;
a central memory that temporarily stores at least one packet of data received at one or more of said plurality of network ports, said central memory including a packet section that temporarily stores received data and is organized into a plurality of sectors, each of said plurality of sectors including a packet sector section and a corresponding sector information section, the central memory also including a network device identification section that stores a plurality of identification entries, each of said plurality of identification entries corresponding to one of the plurality of network devices coupled to one of said plurality of network ports; and
a switch manager coupled to said plurality of network ports and to said central memory, the switch manager controlling data flow between said plurality of network ports and said central memory.
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Accused Products
Abstract
A network switch including a central memory that stores device identification information, port numbers, control information, and packet data received at the ports of the switch. The memory includes a packet section that stores packet data and a device identification section that stores identification entries, where each entry corresponds to a network device coupled to a port of the switch. The switch includes a switch manager to control data flow between the ports and the central memory. Each of the identification entries includes a unique network address to identify one of the network devices and a port number to identify one of the network ports. Each of the identification entries is located within the central memory at a hash address derived by hashing the unique network address. Hash logic receives and hashes each network address to determine a hash address, which is used to access the identification entries. The memory is organized into a chain structure to enable quick access of entries. The switch manager further includes a control memory for storing control registers, including a freepool control register for identifying a freepool chain of memory sectors, a receive control register for identifying a corresponding receive sector chain and a transmit control register for identifying a corresponding transmit packet chain for each of the ports.
168 Citations
27 Claims
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1. A network switch for enabling communication among a plurality of network devices, comprising:
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a plurality of network ports that receive and transmit data;
a central memory that temporarily stores at least one packet of data received at one or more of said plurality of network ports, said central memory including a packet section that temporarily stores received data and is organized into a plurality of sectors, each of said plurality of sectors including a packet sector section and a corresponding sector information section, the central memory also including a network device identification section that stores a plurality of identification entries, each of said plurality of identification entries corresponding to one of the plurality of network devices coupled to one of said plurality of network ports; and
a switch manager coupled to said plurality of network ports and to said central memory, the switch manager controlling data flow between said plurality of network ports and said central memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
each of said plurality of identification entries of said network device identification section including a unique network address identifying one of the plurality of network devices and a port number identifying a corresponding one of said plurality of network ports.
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3. The network switch of claim 2, further comprising:
each of said plurality of identification entries of said network device identification section including a group bitmap number identifying a subset of said plurality of network ports according to a virtual local area network.
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4. The network switch of claim 2, further comprising:
each of said plurality of identification entries of said network device identification section being located within said central memory at a hash address derived by hashing said unique network address.
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5. The network switch of claim 4, wherein said switch manager further comprises:
hash logic that receives and hashes said unique network address to determine said hash address, and that accesses one of said plurality of identification entries within said central memory corresponding to said hash address.
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6. The network switch of claim 5, wherein said hash logic further includes:
a cache memory that retrieves and locally stores a copy of data from said central memory.
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7. The network switch of claim 4, further comprising:
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said network device identification section being organized into a primary section and a chained section, wherein said primary section stores identification entries corresponding to a first occurrence of each hash address, and wherein said chained section stores identification entries corresponding to subsequent and identical hash addresses of different unique network addresses; and
each of said plurality of identification entries further including a link address to access a subsequent identification entry within said chained section if at least one identical hash address occurs.
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8. The network switch of claim 1, further comprising:
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said packet sector section of each of said plurality of sectors storing packet data, where each packet of data is stored in a packet data block; and
said sector information section of each of said plurality of sectors including a sector packet count identifying a number of packet data blocks of data stored in said packet sector section.
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9. The network switch of claim 1, further comprising:
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said switch manager initially organizing said plurality of sectors into a freepool chain of sectors, wherein said sector information section of each of said plurality of sectors includes a link address to a next sector in said freepool chain; and
said switch manager forming a receive sector chain of sectors within said central memory for each of said plurality of network ports receiving at least one packet of data for storage by allocating at least one sector from said freepool chain, linking allocated sectors into a receive sector chain using said link address of each allocated sector, and storing said at least one packet of data received from one of said plurality of network ports into said receive sector chain.
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10. The network switch of claim 9, further comprising:
for each packet of data to be stored, said switch manager determines if a packet sector section of a current sector in said receive sector chain is large enough to store said each packet of data, and if not, allocates a subsequent sector from said freepool chain, and then stores said each packet of data into said current sector and said subsequent sector, if allocated.
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11. The network switch of claim 9, further comprising:
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said packet sector section storing a portion of at least one data packet in a packet data block; and
each said packet data block including a packet block header, said packet block header including a packet length value identifying the amount of data in said packet data block.
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12. The network switch of claim 11, further comprising:
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each said packet block header including a transmit link address to a next packet data block holding subsequent data for one of said plurality of network ports to form a transmit packet chain for said one of said plurality of network ports; and
said switch manager forming a transmit packet chain for each one of said plurality of network ports from which stored data is to be transmitted.
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13. The network switch of claim 12, further comprising:
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said sector information section of each of said plurality of sectors including a sector packet count identifying a number of packet data blocks of data stored in said packet sector section; and
said switch manager retrieving packets of data from packet data blocks within said sectors of said receive sector chains in said central memory in an order specified by a transmit packet chain and providing said retrieved packets of data to a corresponding transmit port, and when said sector packet count indicates a sector is empty, said switch manager replaces said empty sector back into said freepool chain.
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14. The network switch of claim 12, further comprising:
at least one of said packet block headers comprising a broadcast packet header if said packet data is intended to be transmitted to more than one of said plurality of network ports, said broadcast packet header including a plurality of transmit link addresses for maintaining a plurality of transmit packet chains for each of said plurality of network ports from which said packet of data is to be transmitted.
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15. The network switch of claim 12, wherein said switch manager further comprises:
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at least one freepool control register that identifies said freepool chain;
a plurality of receive control registers, each to identify a corresponding receive sector chain for one of said plurality of network ports receiving packet data for storage; and
a plurality of transmit control registers, each to identify a corresponding transmit packet chain for one of said plurality of network ports from which stored packet data is to be transmitted.
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16. The network switch of claim 15, further comprising:
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each of said receive control registers including a receive base pointer, a current data store pointer, a receive packet data length value, a value indicating a number of receive sectors, and a pointer to a last data packet in a corresponding transmit packet chain; and
each of said transmit control registers including a transmit base pointer, a current data retrieval pointer, a transmit packet data length value, and a value indicating a number of transmit packet data blocks.
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17. The network switch of claim 1, further comprising:
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said central memory comprising dynamic random access memory (DRAM); and
said switch manager further including a memory controller that controls data flow between said switch manager and said central memory.
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18. The network switch of claim 17, wherein said memory controller further comprises:
refresh logic that maintains valid data within said central memory.
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19. The network switch of claim 18, wherein said memory controller detects and supports fast page mode DRAM, extended data output DRAM and synchronous mode DRAM.
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20. A network system, comprising:
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a plurality of networks, each including at least one data device for sending and receiving data packets; and
a network switch coupled to said plurality of networks to transfer said data packets, said network switch comprising;
a plurality of network ports that receive and transmit said data packets;
a central memory that temporarily stores said data packets received at one or more of said plurality of network ports, said central memory including a packet section that temporarily stores data and a network device identification section that stores a plurality of identification entries, each of said plurality of identification entries corresponding to one of a plurality of data devices coupled to one of said plurality of network ports, the identification entries being based on hashing an address associated with a corresponding data device; and
a switch manager coupled to said plurality of network ports and to said central memory, the switch manager controlling data flow between said plurality of network ports and said central memory. - View Dependent Claims (21, 22, 23)
each of said plurality of identification entries of said network device identification section being located within said central memory at a hash address derived by hashing a unique network address identifying a corresponding data device.
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22. The network system of claim 21, further comprising:
said network device identification section being organized into a primary section and a chained section, wherein said primary section stores identification entries corresponding to a first occurrence of each hash address, and wherein said chained section stores identification entries corresponding to subsequent occurrences of each hash address.
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23. The network system of claim 20, further comprising:
said packet section being organized into a plurality of sectors, each of said plurality of sectors storing packet data.
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24. A switch for enabling communication among a plurality of devices, comprising:
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a plurality of ports that receive and transmit data, each configured to couple to any one of the plurality of devices;
a central memory that temporarily stores data received at one or more of said plurality of ports, said central memory including a data section that temporarily stores received data and a device identification section that stores a plurality of identification entries, each of said plurality of identification entries being located within said central memory at a hash address derived by hashing a unique address identifying one of the plurality of devices; and
a switch manager coupled to said plurality of ports and to said central memory, the switch manager controlling data flow between said plurality of ports and said central memory. - View Dependent Claims (25, 26, 27)
each of said plurality of identification entries of said device identification section including an address identifying one of the plurality of devices and a port number identifying a corresponding one of said plurality of ports.
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26. The switch of claim 24 further comprising:
said data section being organized into a plurality of sectors, each of said plurality of sectors including a data sector section and a corresponding sector information section.
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27. The switch of claim 24 further comprising:
said switch manager detecting and supporting any one of several different types of memory devices, including fast page mode memory, extended data output memory, and synchronous mode memory.
Specification