CMOS digital optical navigation chip

• US 6,233,368 B1
• Filed: 03/18/1998
• Issued: 05/15/2001
• Est. Priority Date: 03/18/1998
• Status: Expired due to Term

• Current Assignee: Agilent Technologies, Inc., Hewlett-Packard Company (HP Inc.), Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Agilent Technologies, Inc.
• Inventors: Badyal, Rajeev, Knee, Derek L., Anderson, Mark A., Misek, Brian J.
• Primary Examiner(s): Mancuso, Joseph
• Assistant Examiner(s): Kassa, Yosef
• Application Number:
  US09/040,640
• Time in Patent Office: 1,154 Days
• Field of Search: 382/307, 382/312, 382/276, 382/141, 382/321, 257/291, 257/334, 257/292, 257/265, 257/446, 257/204, 375/335, 375/342, 375/326
• US Class Current: 382/307
• CPC Class Codes: H04N 23/68 for stable pick-up of the scene, e.g. compensating for camera body vibrations
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/40 Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor

Abstract

A CMOS digital integrated circuit (IC) chip on which an image is captured, digitized, and then processed on-chip in substantially the digital domain. A preferred embodiment comprises imaging circuitry including a photo cell array for capturing an image and generating a representative analog signal, conversion circuitry including an n-bit successive approximation register (SAR) analog-to-digital converter for converting the analog signal to a corresponding digital signal, filter circuitry including a spatial filter for edge and contrast enhancement of the corresponding image, compression circuitry for reducing the digital signal storage needs, correlation circuitry for processing the digital signal to generate result surface on which a minima resides representing a best fit image displacement between the captured image and previous images, interpolation circuitry for mapping the result surface into x- and y-coordinates, and an interface with a device using the chip, such as a hand-held scanner. The filter circuitry, the compression circuitry, the correlation circuitry and the interpolation circuitry are all advantageously embodied in an on-chip digital signal processor (DSP). The DSP embodiment allows precise algorithmic processing of the digitized signal with almost infinite hold time, depending on storage capability. The corresponding mathematical computations are thus no longer subject to the vagaries of CMOS chip structure processing analog signals. As a result, precise and accurate navigation enables a predictable, reliable and manufacturable design. Parameters may also be programmed into the DSP'"'"'s “software,” making the chip tunable, as well as flexible and adaptable for different applications.

Claims

1. A CMOS integrated circuit chip for capturing and processing images, comprising:

imaging circuitry including a photo cell array for capturing an image projected thereon and for generating an analog signal representative thereof, regions of the array being selectable to be active in operation of the imaging circuitry, the array including a preselected number of photo transistors and a preselected number of photo diodes, each photo cell in the array having a programmable shutter speed, the imaging circuitry further including transfer amplifier circuitry for converting output from the photo cell array into the analog signal;

conversion circuitry including an n-bit SAR analog-to-digital converter for converting the analog signal to a corresponding digital signal;

filter circuitry including a spatial filter for enhancing edges and contrast of the image represented by the digital signal;

compression circuitry for reducing storage needs of the digital signal;

correlation circuitry for processing the digital signal to generate a result surface on which a minima resides, the minima representing a best fit image displacement between the captured image and previous ones thereof;

interpolation circuitry for mapping the image as represented by the result surface into spatially-defining coordinates, wherein selected ones of the filter circuitry, the correlation circuitry and the interpolation circuitry have programmable parameters, values of said parameters corresponding to predesired adaptions of the digital signal; and

interface circuitry for formatting the digital signal so as to be compatible for signal communication with a preselected device.

3. The chip of claim 1, in which the analog-to-digital converter is an 8×

8-bit SAR converter operable at an overall rate of 64 Msamples/sec and 12.5 KFrames/sec.

4. The chip of claim 1, in which the conversion circuitry includes a predetermined number of analog-to-digital converters configured in parallel.

5. The chip of claim 1, in which the compression circuitry is integral with the filter circuitry.

6. The chip of claim 1, in which the compression circuitry compresses the digital signal to 3-4 bits per photo cell in the array.

7. The chip of claim 1, in which the spatially-defining coordinates are orthogonally referenced.

8. The chip of claim 1, in which the spatially-defining coordinates are vector referenced.

9. The chip of claim 1, further comprising bias circuitry.

2. The chip of 1, in which the photo cell array is a 47×

47 array of photo cells.