Method and apparatus for a high-performance embedded memory management unit

• US 6,233,667 B1
• Filed: 03/05/1999
• Issued: 05/15/2001
• Est. Priority Date: 03/05/1999
• Status: Expired due to Term

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Oblock, Gary R., Chan, Jeffrey M. W., Tremblay, Marc, Shaylor, Nik
• Primary Examiner(s): Thai, Tuan V.
• Application Number:
  US09/263,704
• Time in Patent Office: 802 Days
• Field of Search: 711/200, 711/118, 711/154, 711/206, 711/203, 711/220, 711/202
• US Class Current: 711/203
• CPC Class Codes: G06F 12/0223 User address space allocation, e.g. contiguous or non contiguous base addressing
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 12/145 the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism

Abstract

The present invention provides a method and an apparatus for translating a virtual address to a physical address in a computer system. The system receives a virtual address during an execution or a fetch of a program instruction. The system determines if the virtual address is in an upper portion or a lower portion of a virtual address space. If the virtual address is in the lower portion of the virtual address space, the system adds the virtual address to a first base address to produce the physical address. The system also compares the virtual address against an upper bound. If the virtual address has a larger value than the upper bound, the system indicates an illegal access. If the virtual address is in the upper portion of the virtual address space, the system adds the virtual address to a second base address to produce the physical address. The system also compares the virtual address against a lower bound. If the virtual address has a lower value than the lower bound, the system indicates that the access is illegal. Thus, the system provides protection from illegal memory accesses. According to one aspect of the present invention, the system determines if the virtual address falls within portion of the virtual address space that is protected from write accesses. If so, the system disallows write accesses to the virtual address. Thus, the present invention dispenses with paging and reduces the virtual-to-physical address translation process to a simple addition operation. This leads to faster processor clock speeds, and can greatly reduce the cost of designing and fabricating a computer system.

Claims

1. A method for translating a virtual address into a physical address in a computer system, comprising:

receiving the virtual address during an execution or a fetch of a program instruction;

determining if the virtual address is in an upper portion or a lower portion of a virtual address space;

if the virtual address is in the lower portion of the virtual address space,

adding the virtual address to a first base address to produce the physical address, and

comparing the virtual address against an upper bound,

if the virtual address has a larger value than the upper bound, indicating that the access is illegal; and

if the virtual address is in the upper portion of the virtual address space,

adding the virtual address to a second base address to produce the physical address, and

comparing the virtual address against a lower bound,

if the virtual address has a lower value than the lower bound, indicating that the access is illegal,

wherein the method is performed within a memory management unit that is integrated into a microprocessor chip.

2. The method of claim 1, further comprising:

if the virtual address is in the lower portion of the virtual address space, determining if the lower portion of the virtual address space is protected from write accesses, and if so disallowing write accesses to the virtual address; and

if the virtual address is in the upper portion of the virtual address space, determining if the upper portion of the virtual address space is protected from write accesses, and if so disallowing write accesses to the virtual address.

3. The method of claim 1, further comprising disabling address translations during operating system accesses to memory.

4. The method of claim 1, wherein the upper portion of the virtual address space contains read-only library routines.

5. The method of claim 1, wherein the program instruction may include an instruction that bypasses a cache in the computer system for direct memory access (DMA) operations.

6. The method of claim 1, further comprising determining if the access involves a null pointer by comparing the virtual address against a range of null pointer addresses, and if the virtual address falls within the range of null pointer addresses, indicating that the access is illegal.

7. An apparatus for translating a virtual address into a physical address in a computer system, comprising:

an input that receives the virtual address during an execution or a fetch of a program instruction;

an adder that creates a sum of the virtual address and a first base address if the virtual address is in a lower portion of a virtual address space, and that creates a sum of the virtual address and a second base address if the virtual address is in an upper portion of the virtual address space; and

an access validating circuit that indicates an illegal access if the virtual address is in the lower portion of the virtual address space and the virtual address has a larger value than an upper bound, and that indicates an illegal access if the virtual address is in the upper portion of the virtual address space and the virtual address has a lower value than a lower bound;

wherein the apparatus is integrated into a microprocessor chip.

8. The apparatus of claim 7, wherein the adder includes:

a first adding circuit for adding the virtual address to the first base address;

a second adding circuit for adding the virtual address to the second base address, and

a selector circuit that selects between an output of the first adding circuit and an output of the second adding circuit.

9. The apparatus of claim 7, wherein the access validating circuit is configured to determine if the lower portion of the virtual address space is protected from write accesses, and if so to disallow write accesses to the lower portion of the virtual address space, and is configured to determine if the upper portion of the virtual address space is protected from write accesses, and if so to disallow write accesses to the upper portion of the virtual address space.

10. The apparatus of claim 7, further comprising a mechanism that disables address translations during operating system accesses to memory.

11. The apparatus of claim 7, wherein the upper portion of the virtual address space contains read-only library routines.

12. The apparatus of claim 7, further comprising a mechanism that bypasses a cache in the computer system for direct memory access (DMA) operations.

13. The apparatus of claim 7, wherein the access validating circuit is configured to determine if the access involves a null pointer by comparing the virtual address against a range of null pointer addresses, and if the virtual address falls within the range of null pointer addresses, indicating that the access is illegal.

14. An apparatus for translating a virtual address into a physical address in a computer system, comprising:

an input that receives the virtual address during an execution or a fetch of a program instruction;

an adder that creates a sum of the virtual address and a first base address if the virtual address is in a lower portion of a virtual address space, and that creates a sum of the virtual address and a second base address if the virtual address is in an upper portion of the virtual address space, wherein the adder includes,

a first adding circuit for adding the virtual address to the first base address,

a second adding circuit for adding the virtual address to the second base address, and

a selector circuit that selects between an output of the first adding circuit and an output of the second adding circuit; and

an access validating circuit that indicates an illegal access if the virtual address is in the lower portion of the virtual address space and the virtual address has a larger value than an upper bound, and that indicates an illegal access if the virtual address is in the upper portion of the virtual address space and the virtual address has a lower value than a lower bound;

wherein the access validating circuit is configured to determine if the lower portion of the virtual address space is protected from write accesses, and if so to disallow write accesses to the lower portion of the virtual address space, and is configured to determine if the upper portion of the virtual address space is protected from write accesses, and if so to disallow write accesses to the upper portion of the virtual address space, and

wherein the apparatus is integrated into a microprocessor chip.

15. The apparatus of claim 14, wherein the access validating circuit is configured to determine if the access involves a null pointer by comparing the virtual address against a range of null pointer addresses, and if the virtual address falls within the range of null pointer addresses, indicating that the access is illegal.

16. A computer system, comprising:

a central processing unit;

a main memory; and

a first memory management unit within a semiconductor device that contains the central processing unit for translating a virtual address into a physical address, coupled between the central processing unit and the main memory, the first memory management unit comprising,

an adder that creates a sum of the virtual address and a first base address if the virtual address is in a lower portion of a virtual address space, and that creates a sum of the virtual address and a second base address if the virtual address is in an upper portion of the virtual address space, and

an access validating circuit that indicates an illegal access if the virtual address is in the lower portion of the virtual address space and the virtual address has a larger value than an upper bound, and that indicates an illegal access if the virtual address is in the upper portion of the virtual address space and the virtual address has a lower value than a lower bound.

17. The computer system of claim 16, further comprising a cache memory coupled between the central processing unit and the main memory, wherein the first memory management unit is coupled between the central processing unit and the cache memory.

18. The computer system of claim 16, further comprising:

an instruction cache coupled between the central processing unit and the main memory;

a data cache coupled between the central processing unit and the main memory; and

a second memory management unit within the semiconductor device that contains the central processing unit which is configured identically with the first memory management unit;

wherein the first memory management unit is coupled between the central processing unit and the instruction cache, and the second memory management unit is coupled between the central processing unit and the data cache, whereby the first memory management unit performs translations for instruction accesses and the second memory management unit performs translations for data accesses.