Power share controller for providing continuous system peripheral bay access between at least two data processing systems on a data network with no interruption to peripheral bay operation

• US 6,233,692 B1
• Filed: 12/02/1998
• Issued: 05/15/2001
• Est. Priority Date: 12/02/1998
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Villanueva, Peter T.
• Primary Examiner(s): Beausoleil, Robert
• Assistant Examiner(s): PHAN, RAYMOND NGAN
• Application Number:
  US09/203,612
• Time in Patent Office: 895 Days
• Field of Search: 710/101-103, 710/2, 710/129, 710/64, 361/368, 713/310, 713/320, 713/324, 713/323, 713/330, 713/340, 709/214-216, 709/217-219
• US Class Current: 713/324
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24

Abstract

A data processing system such as a server system connected to a data network having a network peripheral bay access feature that enables another server system on the same data network to have access to the system peripheral bay with no operating interruption, when the system main baseboard is disabled. An exemplary server system includes a system peripheral bay supporting at least one peripheral device; a system main baseboard supporting at least one main processor; and a power share board supporting a power share controller for controlling power voltages supplied to the system peripheral bay and the system main baseboard, including automatically switching off electrical connection between the power share board and the system main baseboard when the system main baseboard is disabled, while maintaining the electrical connection between the power share board and the system peripheral bay for peripheral bay operation to enable another server on the same data network to have access to the system peripheral bay with no operating interruption.

Claims

1. A data processing system connected to a data network, comprising:

a peripheral bay which supports at least one peripheral device;

a main baseboard which supports at least one processor; and

a power share board which supports at least a power supply source for supplying power voltages to the peripheral bay and the main baseboard, and a power share controller for controlling the power voltages supplied to the peripheral bay and the main baseboard, including automatically switching off electrical connection to the main baseboard when the main baseboard is disabled, while maintaining electrical connection to the peripheral bay to enable another data processing system on said data network to have access to the peripheral bay without operating interruption.

2. A data processing system as claimed in claim 1, wherein said power share controller provides said power voltages from the power supply source to the processor and the peripheral device during normal system operations, and automatically interrupts said power voltages provided to the processor when the processor is turned off, while maintaining said power voltages provided to the peripheral device for peripheral bay operation with no interruption.

3. A data processing system as claimed in claim 2, wherein said power share controller comprises:

a baseboard switch control circuit which generates switch control signals exhibiting a logic state complementary to a logic state of an input baseboard control signal; and

a baseboard power switch circuit which enables transmission of said power voltages from the power supply source to the processor and the peripheral device in response to the logic state of said switch control signals.

4. A data processing system as claimed in claim 3, wherein said power share board further comprises:

a baseboard remote sense circuit which controls a power supply remote sense feedback from the main baseboard to the power supply source when the processor is turned on; and

a peripheral bay remote sense circuit which controls a power supply remote sense feedback from the peripheral bay to the power supply source when the processor is turned off.

5. A data processing system as claimed in claim 4, wherein said baseboard switch control circuit, during normal system operations, generates baseboard remote sense signals exhibiting a first logic state to activate the baseboard remote sense circuit for said power supply remote sense feedback from the baseboard to the power supply source, in order to maintain all power voltages of the main baseboard in regulation, and simultaneously, generates peripheral remote sense signals exhibiting a second logic state opposite to said first logic state to deactivate the peripheral remote sense circuit.

6. A data processing system as claimed in claim 4, wherein said baseboard switch control circuit, during abnormal system operations, generates baseboard remote sense signals exhibiting a first logic state to deactivate the baseboard remote sense circuit, and simultaneously, generates peripheral remote sense signals exhibiting a second logic state opposite to said first logic state to deactivate the peripheral remote sense circuit for said power supply remote sense feedback from the peripheral bay to the power supply source, in order to maintain all power voltages of the peripheral bay in regulation so as to enable an external server system to have access to the peripheral bay with no operating interruption.

7. A data network, comprising:

a plurality of data processing systems interconnected by a data link, each data processing system including a processor and at least one peripheral device; and

p1 at least one power share controller which provides electrical power to a corresponding data processing system, including at least one peripheral device of said corresponding data processing system, and when the processor of said corresponding data processing system is turned off, said at least one power share controller enables another data processing system on said data network to have access to the peripheral device of said corresponding data processing system with no operating interruption while the processor of said corresponding data processing system is turned off.

8. A data network as claimed in claim 7, wherein each power share controller comprises:

a power supply source which provides said electrical power; and

a power control circuit which provides said electrical power from the power supply source to the processor and to peripheral device of said corresponding data processing system when the processor is turned on, and which provides said electrical power from the power supply source only to the peripheral device when the processor of said corresponding data processing system is turned off.

9. A data network as claimed in claim 7, wherein said plurality of data processing systems comprise server systems.

10. A data network as claimed in claim 8, wherein said power control circuit generates a power supply control signal controlling application of said electrical power to the processor in response to a signal indicating an operational status of the processor.

11. A data network as claimed in claim 8, wherein said power control circuit includes a power switch which, when closed, provides said electrical power from the power supply source to the processor and, when opened, disconnects said electrical power from the power supply source to the processor in response to the signal indicating an operational status of the processor.

12. A data network as claimed in claim 7, wherein said power share controller comprises:

a baseboard switch control circuit which generates switch control signals exhibiting a logic state complementary to a logic state of an input baseboard control signal; and

a baseboard power switch circuit which provides said electrical power from a power supply source to the processor and the peripheral device in response to the logic state of said switch control signals.

13. A data network as claimed in claim 12, wherein said power share controller is integrated on a power share board, and wherein said power share board comprises:

a baseboard remote sense circuit which controls a power supply remote sense feedback from the main baseboard to the power supply source when the processor is turned on; and

a peripheral bay remote sense circuit which controls a power supply remote sense feedback from the peripheral bay to the power supply source when the processor is turned off.

14. A data network as claimed in claim 12, wherein said baseboard switch control circuit, during normal system operations, generates baseboard remote sense signals exhibiting a first logic state to activate the baseboard remote sense circuit for said power supply remote sense feedback from the baseboard to the power supply source, in order to maintain all power voltages of the main baseboard in regulation, and simultaneously, generates peripheral remote sense signals exhibiting a second logic state opposite to said first logic state to deactivate the peripheral remote sense circuit.

15. A data network as claimed in claim 13, wherein said baseboard switch control circuit, during abnormal system operations, generates baseboard remote sense signals exhibiting a first logic state to deactivate the baseboard remote sense circuit, and simultaneously, generates peripheral remote sense signals exhibiting a second logic state opposite to said first logic state to deactivate the peripheral remote sense circuit for said power supply remote sense feedback from the peripheral bay to the power supply source, in order to maintain all power voltages of the peripheral bay in regulation so as to enable an external server system to have access to the peripheral bay with no operating interruption.

16. A method for ensuring peripheral bay access of a data processing system including a main baseboard supporting a processor and a peripheral bay supporting at least one peripheral device on a data network, comprising the steps of:

determining whether a main baseboard of the data processing system is enabled or disabled;

when the main baseboard of the data processing system is enabled, maintaining electrical power to both the main baseboard and the peripheral bay in regulation; and

when the main baseboard of the data processing system is disabled, interrupting said electrical power provided to the main baseboard while maintaining said electrical power to the peripheral bay in regulation to enable an external system on said data network to have access to the peripheral bay of the data processing system with no operating interruption.

17. A method as claimed in claim 16, wherein said data processing system corresponds to a server system on a data network, and comprises:

a peripheral bay which supports at least one peripheral device;

a main baseboard which supports at least one processor; and

a power share controller which controls application of said electrical power to the peripheral bay and the main baseboard, including automatically switching off electrical connection to the main baseboard when the main baseboard is disabled, while maintaining the electrical connection to the peripheral bay to enable another data processing system on said data network to have access to the peripheral bay with no operating interruption.

18. A method as claimed in claim 17, wherein said data processing system further comprises:

a power share board supporting said power share controller and containing at least one power supply source for providing said electrical power to the peripheral bay and the main baseboard, said power share controller providing said electrical power from the power supply source to the processor and the peripheral device during normal system operations, and automatically interrupting said electrical power provided to the processor when the processor is turned off, while maintaining said power voltages provided to the peripheral device for peripheral bay operation with no interruption.

19. A method as claimed in claim 18, wherein said power share controller comprises:

a baseboard switch control circuit which generates switch control signals exhibiting a logic state complementary to a logic state of an input baseboard control signal; and

a baseboard power switch circuit which enables transmission of said power voltages from the power supply source to the processor and the peripheral device in response to the logic state of said switch control signals.

20. A method as claimed in claim 19, wherein said power share board further comprises:

a baseboard remote sense circuit which controls a power supply remote sense feedback from the main baseboard to the power supply source when the processor is turned on; and

a peripheral bay remote sense circuit which controls a power supply remote sense feedback from the peripheral bay to the power supply source when the processor is turned off.

21. A method as claimed in claim 20, wherein said baseboard switch control circuit, during normal system operations, generates baseboard remote sense signals exhibiting a first logic state to activate the baseboard remote sense circuit for said power supply remote sense feedback from the baseboard to the power supply source, in order to maintain all power voltages of the main baseboard in regulation, and simultaneously, generates peripheral remote sense signals exhibiting a second logic state opposite to said first logic state to deactivate the peripheral remote sense circuit.

22. A method as claimed in claim 20, wherein said baseboard switch control circuit, during abnormal system operations, generates baseboard remote sense signals exhibiting a first logic state to deactivate the baseboard remote sense circuit, and simultaneously, generates peripheral remote sense signals exhibiting a second logic state opposite to said first logic state to deactivate the peripheral remote sense circuit for said power supply remote sense feedback from the peripheral bay to the power supply source, in order to maintain all power voltages of the peripheral bay in regulation so as to enable an external server system to have access to the peripheral bay with no operating interruption.

23. A data processing system, comprising:

one or more peripheral devices;

a processor; and

one or more power supply sources which supply power voltages to one or more peripheral devices and to the processor; and

a power share controller which controls the power voltages supplied to one or more peripheral devices and to the processor so as to allow another data processing system to have access to one or more peripheral devices even when the power voltages supplied to the processor have been disabled, said power share controller comprising;

a baseboard switch control circuit which generates switch control signals exhibiting a logic state complementary to a logic state of an input baseboard control signal; and

a baseboard power switch circuit which enables transmission of said power voltages from one or more power supply sources to one or more peripheral devices and to the processor in response to the logic state of said switch control signals.

24. A data processing system as claimed in claim 23, wherein said power share controller provides power voltages to one or more peripheral devices and to the processor during normal system operations, and automatically interrupts said power voltages provided to the processor when the processor is turned off, while maintaining said power voltages provided to one or more peripheral devices for peripheral device operations without interruption.

25. A data processing system as claimed in claim 23, wherein said one or more peripheral devices include, but are not limited to, magnetic or optical information storage devices and small computer system interface (SCSI) devices.

26. A data processing system as claimed in claim 25, wherein said power share board further comprises:

a baseboard remote sense circuit which controls a power supply remote sense feedback from the processor to one or more power supply sources when the processor is turned on; and

a peripheral bay remote sense circuit which controls a power supply remote sense feedback from one or more peripheral devices to one or more power supply sources when the processor is turned off.

27. A data processing system as claimed in claim 25, wherein said baseboard switch control circuit, during normal system operations, generates baseboard remote sense signals exhibiting a first logic state to activate the baseboard remote sense circuit for said power supply remote sense feedback from the processor back to one or more power supply sources so as to maintain all power voltages of the processor in regulation, and simultaneously, generates peripheral remote sense signals exhibiting a second logic state opposite to said first logic state to deactivate the peripheral remote sense circuit.

28. A data processing system as claimed in claim 25, wherein said baseboard switch control circuit, during abnormal system operations, generates baseboard remote sense signals exhibiting a first logic state to deactivate the baseboard remote sense circuit, and simultaneously, generates peripheral remote sense signals exhibiting a second logic state opposite to said first logic state to deactivate the peripheral remote sense circuit for said power supply remote sense feedback from one or more peripheral devices back to one or more power supply sources so as to maintain all power voltages of one or more peripheral devices in regulation so as to enable an external system to have access to one or more peripheral devices without operating interruption.