Technique for partitioning data to correct memory part failures
First Claim
Patent Images
1. A memory system comprising:
- a plurality of first components configured to store a data block, wherein said data block includes a plurality of data bits and a plurality of check bits, and wherein each bit of said data block is assigned to one of said plurality of first components;
a plurality of second components configured to transfer the bits of said data block, wherein each bit of said data block is assigned to one of said plurality of second components;
an error detection circuit coupled to said first components and said second components;
wherein said data bits and said check bits are grouped to form a plurality of logical groups, and wherein each logical group includes at most one bit assigned to a given one of said plurality of first components and at most one bit assigned to a given one of said plurality of second components;
wherein said error detection circuit is configured to;
generate one or more check bits of a given one of said logical groups from data bits of the given one of said logical groups;
verify the accuracy of the data bits of the given one of said logical groups using the check bits of the given one of said logical groups; and
wherein numbers of bits in each of said logical groups are selected to optimize a ratio of a number of said check bits to a number of said data bits.
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Abstract
The bits of a data block are assigned to a plurality of logical groups such that at most one bit corresponding to a component is assigned to a logical group. This assignment ensures that a component failure may introduce at most one bit error to a logical group. A number of bits in a logical group is selected to reduce the number of check bits for a given number of data bits. Error correction may be performed within each logical group to correct single errors within the logical group. Because each logical group is assigned at most one bit corresponding to a component, component failures may be detected and corrected.
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Citations
30 Claims
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1. A memory system comprising:
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a plurality of first components configured to store a data block, wherein said data block includes a plurality of data bits and a plurality of check bits, and wherein each bit of said data block is assigned to one of said plurality of first components;
a plurality of second components configured to transfer the bits of said data block, wherein each bit of said data block is assigned to one of said plurality of second components;
an error detection circuit coupled to said first components and said second components;
wherein said data bits and said check bits are grouped to form a plurality of logical groups, and wherein each logical group includes at most one bit assigned to a given one of said plurality of first components and at most one bit assigned to a given one of said plurality of second components;
wherein said error detection circuit is configured to;
generate one or more check bits of a given one of said logical groups from data bits of the given one of said logical groups;
verify the accuracy of the data bits of the given one of said logical groups using the check bits of the given one of said logical groups; and
wherein numbers of bits in each of said logical groups are selected to optimize a ratio of a number of said check bits to a number of said data bits. - View Dependent Claims (2, 3, 4)
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5. A system comprising:
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a processor;
a bus;
a memory coupled to said processor and said bus, comprising;
a plurality of first components configured to store a data block, wherein said data block includes a plurality of data bits and a plurality of check bits, and wherein each bit of said data block is assigned to one of said plurality of first components;
a plurality of second components configured to transfer bits of said data block, wherein each bit of said data block is assigned to one of said plurality of second components;
an error detection circuit coupled to said first components and said second components;
wherein said data bits and said check bits are grouped to form a plurality of logical groups, and wherein each of said logical groups includes at most one bit assigned to a given one of said plurality of first components and at most one bit assigned to a given one of said plurality of second components;
wherein said error detection circuit is configured to;
generate one or more check bits of a given one of said logical groups from data bits of the given one of said logical groups;
verify the accuracy of the data bits of the given one of said logical groups using the check bits of the given one of said logical groups; and
wherein numbers of bits in each of said logical groups are selected to optimize a ratio of a number of said check bits to a number of said data bits. - View Dependent Claims (6, 7, 8)
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9. A method of detecting errors in a data block of a computer system that includes a plurality of components, comprising:
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assigning a plurality of bits of said data block to a plurality of logical groups such that each of said logical groups includes at most one bit corresponding to a given one of said plurality of components, wherein said plurality of bits of said data block includes a plurality of data bits and a plurality of check bits; and
performing error correction on bits within each logical group of said plurality of logical groups, wherein said error correction is performed upon detection of at least one error in said bits;
wherein a number of bits in each of said logical groups is selected to decrease a number of check bits in said data block. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A method of detecting errors in a data block of a computer system that includes a plurality of first components and a plurality of second components wherein bits of said data block correspond to a first component and a second component, said method comprising:
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assigning said bits of said data block to a plurality of logical groups such that at most one bit corresponding to a given one of said plurality of first components is assigned to a first logical group of said plurality of logical groups and at most one bit corresponding to a given one of said plurality of second components is assigned to said first logical group; and
performing error detection on bits within said first logical group, wherein said first logical group includes a plurality of data bits and a plurality of check bits;
wherein a number of bits in said first logical group is selected to decrease a number of check bits in said data block. - View Dependent Claims (18, 19, 20, 21, 22)
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23. An apparatus for detecting errors in a data block of a computer system that includes a plurality of components, comprising:
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means for assigning a plurality of bits of said data block to a plurality of logical groups such that at most one bit of said plurality of bits corresponding to a given one of said components is assigned to any given one of said logical groups, wherein said plurality of bits of said data block includes a plurality of data bits and a plurality of check bits; and
means for performing error correction on bits within each of said logical groups, wherein said error correction is performed upon detection of at least one error in said bits;
wherein a number of bits in each of said logical groups is selected to decrease a number of check bits in said data block. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30)
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Specification