Method and apparatus for producing signal processing circuits in the delta sigma domain

• US 6,234,658 B1
• Filed: 06/07/1996
• Issued: 05/22/2001
• Est. Priority Date: 06/07/1996
• Status: Expired due to Term

• Current Assignee: Powerprecise Solutions
• Original Assignee: Duality Semiconductor, Inc.
• Inventors: Houldsworth, John
• Primary Examiner(s): Smith, Mathew
• Assistant Examiner(s): DO, THUAN V
• Application Number:
  US08/660,361
• Time in Patent Office: 1,810 Days
• Field of Search: 364/489, 364/490, 364/491, 341/118
• US Class Current: 716/101
• CPC Class Codes: G06F 17/10 Complex mathematical operations function generation by table look-up G06F1/03; evaluation of elementary functions by calculation G06F7/544
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

The present invention is directed to providing a generalized system and method for enabling circuit design and fabrication in the delta sigma domain. In accordance with exemplary embodiments, a framework for such a system is based on a library of generalized operators that can receive multiple inputs, and that can be randomly chained together. Further, the operators are specifically configured to guarantee valid (e.g., bounded and/or stable) results, and to provide closure within the delta sigma domain; that is, to produce valid intermediate results in the delta sigma domain. Linear operators are configured to provide closure by complying with at least two criteria: (1) with respect to linear operators, at least one of (a) the inputs and (b) the output of a portion of the operator used to implement a mathematical function is scaled (e.g., normalized) to guarantee valid results; and (2) outputs from each mathematical operation are remodulated into a single bit stream in the delta sigma domain. Further, nonlinear operators such as multiplication operators, are configured with an eye toward producing valid results in the delta sigma domain. For example, with respect to nonlinear operators such as multipliers, at least one operand is restricted to being a non-delta sigma input (i.e., quantization noise-free). As with linear operators, the outputs from portions of nonlinear operators used to implement mathematical operations are remodulated to a single bit stream in the delta sigma domain.

Claims

1. A computer-implemented library for implementing digital signal processing in the delta sigma domain comprising:

at least two functional operators, each of said operators having at least one of a scaled input and a scaled output for producing a valid result in the delta sigma domain, each of said at least two functional operators further including a remodulator to produce at least one bit stream output of one bit in said delta sigma domain; and

an output for selectively supplying each of said at least two functional operators to an analog logic translator which correlates said at least two functional operators to an analog function.

2. A computer-implemented library according to claim 1, wherein at least one of said at least two functional operators implements in a linear function, said library further comprising:

at least one additional operator for implementing a nonlinear function.

3. A computer-implemented library according to claim 2, wherein said nonlinear function is a multiplication.

4. A computer-implemented library according to claim 3, wherein said at least one additional operator further includes:

means for calculating parameters associated with an equation of a line tangential to a point of said nonlinear function.

5. A computer-implemented library according to claim 2, wherein said linear function is integration.

6. A computer-implemented library according to claim 5, wherein said at least one functional operator for implementing said linear function of integration further includes:

a comparator having a negative feedback path which includes a differentiator.

7. A computer-implemented library according to claim 1, wherein at least one of said at least two functional operators further includes:

means for scaling a sign bit of an input bit stream to said at least one functional operator.

8. A computer-implemented library according to claim 1, wherein said remodulator further includes:

at least one discrete time integrator having a parameterized fractional content

9. A computer-implemented library according to claim 1, wherein at least one of said at least two functional operators is implemented as a logic state machine.

10. A computer-implemented system for providing a linear operator for implementing an analog function in the delta sigma domain comprising:

means for performing a mathematical operation on a first input signal and a second input signal to the operator and for scaling at least one of said first input signal and an output of the mathematical operation; and

means for remodulating said output of the mathematical operation to maintain said output as at least one bit stream of one bit samples in the delta sigma domain.

11. The computer-implemented system according to claim 10, wherein said operator performs an addition function.

12. The computer-implemented system according to claim 10, wherein said operator performs a subtraction function.

13. The computer-implemented system according to claim 10, wherein said operator performs a comparator function.

14. The computer-implemented system according to claim 10, wherein said operator performs a linear scaling function.

15. The computer-implemented system according to claim 10, wherein said means for remodulating further includes.

at least one discrete time integrator having a parameterized fractional content.

16. The computer-implemented system according to claim 10, wherein said analog function is a differentiation function.

17. The computer-implemented system according to claim 10, wherein said analog function is an integration function.

18. A computer-implemented system for providing a nonlinear operator for implementing an analog multiplication function on a delta sigma input to produce an output in the delta sigma domain comprising:

means for receiving a first input signal as an operand, said first input signal being a bitstream including quantization noise;

means for receiving a second input signal to said nonlinear operator as a multibit input with reduced quantization noise relative to said first input signal;

means for performing an analog multiplication function on said first and second input signals; and

means for remodulating an output of said analog multiplication function performing means to maintain said output as at least one bit stream of one bit samples in said delta signal domain.

19. The computer-implemented system according to claim 18, wherein said analog multiplication function is a scaling function.

20. The computer-implemented system according to claim 18, wherein said second input signal is derived from a nonlinear function.

21. A computer-implemented system for providing an operator for implementing an analog integration function in the delta sigma domain comprising:

means for receiving a first input signal in the delta sigma domain as an operand, said first input signal including quantization noise; and

means for comparing said first input signal with a second signal, said second signal being produced via a negative feedback path to a comparator which includes a differentiator.

22. A computer-implemented system according to claim 21, wherein said first input signal is a bit stream of one bit samples in the delta sigma domain, said operator further including:

a remodulator for producing an output of said comparing means as a bit stream in the delta sigma domain.

23. A computer-implemented system according to claim 21, further including:

means for scaling said first input signal prior to comparing said first input signal with said second signal.