Chip scale package and method for manufacturing the same using a redistribution substrate

• US 6,235,552 B1
• Filed: 01/12/2000
• Issued: 05/22/2001
• Est. Priority Date: 07/09/1999
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kwon, Yong Hwan, Kang, Sa Yoon
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Anya, Igwe U.
• Application Number:
  US09/482,160
• Time in Patent Office: 496 Days
• Field of Search: 438/106, 438/107, 438/114, 438/118, 438/123, 438/127
• US Class Current: 438/106
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02319 by using a preform
• CPC Class Codes: H01L 2224/0233 Structure of the redistribution layers
• CPC Class Codes: H01L 2224/02333 being a bump
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/03003 for holding or transferring a preform
• CPC Class Codes: H01L 2224/03438 the preform being at least partly pre-patterned
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15747 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A method for manufacturing a chip scale package includes: providing a redistribution substrate; attaching a semiconductor wafer to the redistribution substrate; forming external terminals on the redistribution substrate; and separating the semiconductor wafer and the redistribution substrate into individual integrated circuits. The method can further include forming a buffer layer by filling a gap between the semiconductor wafer and the redistribution substrate with a dielectric material. Another method is the same as the method described above except that instead of the semiconductor wafer, individual integrated circuit chips attach to the redistribution substrate. Meanwhile, a semiconductor package includes: a semiconductor integrated circuit having chip pads formed thereon; interconnection bumps overlying on the chip pads; a patterned metal layer connecting to the interconnetion bumps; a first dielectric layer under the patterned metal layer; a second dielectric layer overlying on the patterned metal layer; and terminal pads connecting to the patterned metal layer. The semiconductor package can further include external terminals connecting to the terminal pads, a third dielectric layer filling a gap between the first dielectric layer and the semiconductor integrated circuit.

Claims

1. A method for manufacturing a semiconductor package, comprising:

providing a redistribution substrate comprising a substrate base, a plurality of terminal pads formed on the substrate base, a plurality of interconnection bumps, and a patterned metal layer which connects the interconnection bumps to the respective terminal pads;

attaching a semiconductor wafer, on which a plurality of integrated circuits and a plurality of chip pads are formed, to the redistribution substrate, such that the interconnection bumps of the redistribution substrate contact the chip pads of the semiconductor wafer;

forming a plurality of external terminals on the respective terminal pads of the redistribution substrate; and

separating the semiconductor wafer and the redistribution substrate into individual semiconductor packages, each semiconductor package including an integrated circuit having a corresponding portion of the redistribution substrate attached thereon.

2. The method of claim 1, wherein providing the redistribution substrate comprises:

forming a first dielectric layer having a plurality of first openings on the substrate base;

forming the terminal pads on the substrate base inside the first openings;

forming the patterned metal layer on the first dielectric layer, the patterned metal layer connecting to the terminal pads;

forming a second dielectric layer on the patterned metal layer and the first dielectric layer, the second dielectric layer including a plurality of second openings; and

forming the interconnection bumps on the patterned metal layer exposed through the second openings, wherein the interconnection bumps electrically connect to the respective terminal pads through the patterned metal layer.

3. The method of claim 1, wherein forming the external terminals comprises:

removing the substrate base so as to expose the terminal pads; and

forming a plurality of protruding components on the respective terminal pads.

4. The method of claim 1, wherein forming the external terminals comprises patterning the substrate base so that portions of the substrate base remain on the terminal pads, wherein the remaining portions of the substrate base are used as the external terminals.

5. The method of claim 1, further comprising forming a buffer layer by filling a gap between the semiconductor wafer and the redistribution substrate with a dielectric material.

6. A method for manufacturing a semiconductor package, comprising:

providing a redistribution substrate comprising a substrate base, a plurality of terminal pads formed on the substrate base, a plurality of interconnection bumps, and a patterned metal layer which connects the interconnection bumps to the respective terminal pads;

attaching a plurality of semiconductor integrated circuit chips, each of which has a plurality of chip pads formed thereon, to the redistribution substrate, such that the interconnection bumps of the redistribution substrate contact the chip pads of the semiconductor chips;

patterning the substrate base so that portions of the substrate base remain on the terminal pads, wherein the remaining portions of the substrate base are used as the external terminals; and

separating the redistribution substrate so as to produce individual semiconductor packages, each of which includes an integrated circuit chip having a corresponding portion of the redistribution substrate attached thereon.

7. The method of claim 6, wherein providing the redistribution substrate comprises:

forming a first dielectric layer having a plurality of first openings on the substrate base;

forming the terminal pads on the substrate base inside the first openings;

forming the patterned metal layer on the first dielectric layer, the patterned metal layer connecting to the terminal pads;

forming a second dielectric layer having a plurality of second openings on the patterned metal layer and the first dielectric layer; and

forming the interconnection bumps on the patterned metal layer exposed through the second openings, wherein the interconnection bumps electrically connect to the respective terminal pads through the patterned metal layer.

8. The method of claim 6, further comprising forming a buffer layer by filling a gap between the integrated circuit chips and the redistribution substrate with a dielectric material.