Method for fabricating stackable chip scale semiconductor package

• US 6,235,554 B1
• Filed: 05/24/1999
• Issued: 05/22/2001
• Est. Priority Date: 11/27/1995
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Farnworth, Warren M., Wood, Alan G., Akram, Salman
• Primary Examiner(s): Picardat, Kevin M.
• Application Number:
  US09/316,997
• Time in Patent Office: 729 Days
• Field of Search: 438/109, 438/113, 438/121, 438/125, 438/618, 438/637, 438/672, 438/675, 257/685, 257/686, 257/698
• US Class Current: 438/109
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/06136 Covering only the central area of the surface to be connected, i.e. central arrangements
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/8114 Guiding structures outside the body
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49883 : the conductive materials containing organic materials or pastes, e.g. for thick films for printed circuits H05K1/092
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15156 : Side view
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18165 : of a wire bonded chip
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A stackable chip scale semiconductor package and a method for fabricating the package are provided. The package includes a substrate having a die mounting site wherein a semiconductor die is mounted. The package also includes first contacts formed on a first surface of the substrate, and second contacts formed on an opposing second surface of the substrate. Conductive vias in the substrate electrically connect the first contacts to the second contacts. In addition, the first contacts and the second contacts have a mating configuration, such that a second package can be stacked on and electrically connected to the package. The method for fabricating the package includes the steps of: laser machining and etching the vias, forming an insulating layer in the vias, and then depositing a conductive material within the vias.

Claims

1. A method for fabricating a semiconductor package comprising:

providing a substrate having a first surface and an opposing second surface;

laser machining a plurality of vias in the substrate from the first surface to the second surface;

at least partially filling the vias with a conductive material to form conductive vias;

forming a plurality of first contacts on the first surface in electrical communication with the conductive vias;

forming a plurality of second contacts on the second surface in electrical communication with the conductive vias; and

mounting a die to the substrate in electrical communication with the first contacts or the second contacts.

2. The method of claim 1 wherein the substrate comprises silicon.

3. The method of claim 1 further comprising following laser machining of the vias etching the vias.

4. The method of claim 1 wherein the second contacts are configured to retain and electrically engage third contacts substantially identical to the first contacts.

5. The method of claim 1 further comprising providing a second package having third contacts substantially identical to the first contacts, then stacking the second package on the package with the second contacts retaining and electrically engaging the third contacts.

6. A method for fabricating a semiconductor package comprising:

providing a silicon substrate comprising a first surface and an opposing second surface;

laser machining a via through the substrate from the first surface to the second surface;

etching the via;

forming an insulating layer in the via;

at least partially filling the via with a conductive material to form a conductive via;

forming a first contact on the first surface in electrical communication with the conductive via;

forming a second contact on the second surface in electrical communication with the conductive via, the second contact and the first contact having a mating configuration; and

mounting a die to the substrate in electrical communication with the first contact or the second contact.

7. The method of claim 6 wherein the second contacts are configured to retain and electrically engage third contacts substantially similar to the first contacts.

8. The method of claim 6 wherein the first contacts comprise bumps and the second contacts comprise recesses.

9. A method for fabricating a semiconductor package comprising:

providing a substrate having a first surface and an opposing second surface;

forming a conductive via through the substrate from the first surface to the second surface by laser machining a via and at least partially filling the via with a conductive material;

forming a first contact on the first surface in electrical communication with the conductive via;

forming a second contact on the second surface in electrical communication with the conductive via;

mounting a die to the substrate in electrical communication with the first contact or the second contact; and

stacking the substrate on a second substrate, the second substrate having a third contact in electrical communication with a second die on the second substrate, the third contact substantially identical to the first contact and bonded to the second contact.

10. The method of claim 9 wherein the substrate comprises silicon and forming the conductive via comprises etching the via following laser machining.

11. The method of claim 9 wherein the substrate comprises silicon and forming the conductive via comprises etching the via, forming an insulating layer on a sidewall of the via, and depositing a conductive layer in the via.

12. A method for fabricating a semiconductor package comprising:

providing a silicon substrate having a first surface and an opposing second surface;

laser machining a plurality of vias in the substrate extending from the first surface to the second surface;

etching the vias;

depositing a conductive material within the vias to form conductive vias;

forming first contacts on the first substrate in electrical communication with the conductive vias;

forming second contacts on the second substrate in electrical communication with the conductive vias, the second contacts configured to retain and electrically engage the first contacts;

mounting a die to the substrate; and

forming electrical paths between the die and the first contacts or the second contacts.

13. The method of claim 12 wherein the first contacts comprise bumps and the second contacts comprise recesses.

14. The method of claim 12 wherein the first contacts or the second contacts comprise a conductive polymer.

15. The method of claim 12 wherein the first contacts comprise cylindrical tip portions and the second contacts comprise openings for receiving the tip portions.

16. A method for fabricating a semiconductor package comprising:

providing a first wafer and a second wafer;

forming a plurality of packages on the first wafer and the second wafer, each package including a substrate comprising a portion of the first wafer or the second wafer, and a die in electrical communication with a plurality of first contacts on a first side of the substrate, and with a plurality of second contacts on a second side of the substrate;

stacking the first wafer to the second wafer with selected first contacts on the first wafer in electrical communication with selected second contacts on the second wafer; and

cutting the first wafer and the second wafer to form a plurality of stacked packages.

17. The method of claim 16 wherein the first wafer comprises silicon and the second wafer comprises silicon.

18. The method of claim 17 wherein forming the packages comprises laser machining conductive vias on the substrate in electrical communication with the first contacts and the second contacts.

19. The method of claim 18 wherein the selected first contacts are configured to retain and electrically engage the selected second contacts.

20. The method of claim 19 wherein the selected first contacts comprise bumps and the selected second contacts comprise recesses.

21. A method for fabricating a semiconductor package comprising:

providing a first package comprising a first contact on a first surface thereof, and a second contact on a second surface thereof, and a conductive via electrically connecting the first contact to the second contact;

providing a second package substantially identical to the first package and with the second contact on the second package configured to retain and electrically engage the first contact on the first package; and

stacking the first package on the second package with the second contact on the second package retaining and electrically engaging the first contact on the first package.

22. The method of claim 21 further comprising forming a conductive polymer layer between the first contact on the first package and the second contact on the second package prior to the stacking step.

23. The method of claim 21 wherein the first contact comprises a bump and the second contact comprises a recess sized to retain the bump.

24. The method of claim 21 wherein the first contact comprises a tip portion and the second contact comprise an opening sized to retain the tip portion.

25. The method of claim 21 wherein the first package is contained on a first wafer and the second package is contained on a second wafer, and further comprising singluating the first package from the first wafer and the second package from the second wafer following the stacking step.