Method for manufacturing stacked capacitor

• US 6,235,579 B1
• Filed: 11/30/1999
• Issued: 05/22/2001
• Est. Priority Date: 10/18/1999
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lou, Chine-Gie
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): Brewster, William M.
• Application Number:
  US09/451,384
• Time in Patent Office: 539 Days
• Field of Search: 438/3, 438/253, 438/396
• US Class Current: 438/253
• CPC Class Codes: H01L 21/7687 Thin films associated with contacts of capacitors
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor

Abstract

A method of manufacturing a stacked capacitor. A first dielectric layer is formed over a substrate. A first nitride layer is formed on the first dielectric layer. A storage node contact hole is formed to penetrate through the first nitride layer and the first dielectric layer and to expose a portion of the substrate. A first conductive plug is formed in the storage node contact hole. A second dielectric layer is formed on the first nitride layer and the first conductive plug. A second nitride layer is formed on the second dielectric layer. A contact hole is formed to penetrate through the second nitride layer and the second dielectric layer and to expose portions of the first conductive plug. A second conductive plug is formed in the contact hole with a surface level lower than a surface level of the second nitride layer. A metal barrier layer is formed on the second conductive plug and fills the contact hole. A first metal layer is formed over the substrate. The first metal layer, the second nitride layer and the second dielectric layer are patterned to form a storage node. The storage node comprises the second conductive plug and the metal barrier layer. A metal spacer is formed on the sidewall of the storage node. A third dielectric layer is formed over the substrate. A second metal layer is formed on the third dielectric layer.

Claims

1. A method of manufacturing a stacked capacitor, comprising the steps of:

proving a substrate;

forming a first dielectric layer over the substrate;

forming a first nitride layer on the first dielectric layer;

forming a storage node contact hole penetrating through the first nitride layer and the first dielectric layer to expose a portion of the substrate;

forming a first conductive plug in the storage node contact hole;

forming a second dielectric layer on the first nitride layer and the first conductive plug;

forming a second nitride layer on the second dielectric layer;

forming a contact hole penetrating through the second nitride layer and the second dielectric layer to expose a portion of the first conductive plug;

forming a second conductive plug in the contact hole with a surface level lower than a surface level of the second nitride layer;

forming a metal barrier layer on the second conductive plug and filling the contact hole;

forming a first metal layer over the substrate;

patterning the first metal layer, the second nitride layer and the second dielectric layer to form a storage node, wherein the storage node comprises the second conductive plug and the metal barrier layer;

forming a metal spacer on the sidewall of the storage node;

forming a third dielectric layer over the substrate; and

forming a second metal layer on the third dielectric layer.

2. The method of claim 1, wherein the first dielectric layer and the second dielectric layer are made of silicon oxide.

3. The method of claim 1, wherein the first dielectric layer and the second dielectric layer are formed by chemical vapor deposition.

4. The method of claim 1, wherein a thickness of the second nitride layer is about 500-1500 angstroms.

5. The method of claim 1, wherein the first nitride layer is made of silicon oxynitride.

6. The method of claim 1, wherein the first nitride layer and the second nitride layer are made of silicon nitride.

7. The method of claim 1, wherein the first conductive plug and second conductive plug are made of polysilicon.

8. The method of claim 1, wherein the metal barrier layer is made of titanium nitride, tungsten nitride or tantalum nitride.

9. The method of claim 1, wherein the first metal layer is made of platinum.

10. The method of claim 1, wherein a thickness of the first metal layer is about 800-2000 angstroms.

11. The method of claim 1, wherein the step of forming the metal spacer comprises the steps of:

forming a third metal layer over the substrate; and

performing an etching back process to form the metal spacer.

12. The method of claim 11, wherein a thickness of the third metal layer is about 300-800 angstroms.

13. The method of claim 1, wherein the metal spacer is made of platinum.

14. The method of claim 1, wherein the third dielectric layer is made of barium titanate.

15. The method of claim 1, wherein the third dielectric layer is made of barium strontium titanate.

16. A method of manufacturing a stacked capacitor, comprising the steps of:

proving a substrate;

forming a first silicon oxide layer over the substrate;

forming a first silicon nitride layer on the first layer;

forming a storage node contact hole penetrating through the first silicon nitride layer and the first silicon oxide layer to expose a portion of the substrate;

forming a first polysilicon plug in the storage node contact hole;

forming a second silicon oxide layer on the first silicon nitride layer and the first polysilicon plug;

forming a second silicon nitride layer on the second silicon oxide layer;

forming a contact hole penetrating through the second silicon nitride layer and the second silicon oxide layer to expose portions of the first polysilicon plug;

forming a second polysilicon plug in the contact hole with a surface level lower than a surface level of the second silicon nitride layer;

forming a metal barrier layer on the second conductive plug and filling the contact hole;

forming a platinum layer over the substrate;

patterning the platinum layer, the second silicon nitride layer and the second silicon oxide layer to form a storage node, wherein the storage node comprises the second polysilicon plug and the metal barrier layer;

forming a metal spacer on the sidewall of the storage node;

forming a barium strontium titanate layer over the substrate; and

forming a first metal layer on the barium strontium titanate layer.

17. The method of claim 16, wherein the first silicon nitride layer and the second silicon nitride layer are formed by chemical vapor deposition.

18. The method of claim 16, wherein a thickness of the second silicon nitride layer is about 500-1500 angstroms.

19. The method of claim 16, wherein the metal barrier layer is made of titanium nitride, tungsten nitride or tantalum nitride.

20. The method of claim 16, wherein a thickness of the platinum layer is about 800-2000 angstroms.

21. The method of claim 16, wherein the step of forming the metal spacer comprises the steps of:

forming a second metal layer over the substrate; and

performing an etching back process to form the metal spacer.

22. The method of claim 21, wherein a thickness of the second metal layer is about 300-800 angstroms.

23. The method of claim 16, wherein the metal spacer is made of platinum.