Thin floating gate and conductive select gate in situ doped amorphous silicon material for NAND type flash memory device applications

• US 6,235,586 B1
• Filed: 07/13/1999
• Issued: 05/22/2001
• Est. Priority Date: 07/13/1999
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Au, Kenneth Wo-Wai, Chang, Kent Kuohua, Fang, Hao
• Primary Examiner(s): BOOTH, RICHARD A
• Application Number:
  US09/352,801
• Time in Patent Office: 679 Days
• Field of Search: 438/257-267, 438/593-599
• US Class Current: 438/258
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

In one embodiment, the present invention relates to a method of forming a NAND type flash memory device, involving the steps of growing a first oxide layer over at least a portion of a substrate, the substrate including a flash memory cell area and a select gate area; removing a portion of the first oxide layer in the flash memory cell area of the substrate; growing a second oxide layer over at least a portion of the substrate in the flash memory cell area and over at least a portion of the a first oxide layer in the select gate area; depositing a first in situ doped amorphous silicon layer over at least a portion of the second oxide layer, the first in situ doped amorphous silicon layer having a thickness from about 400 Å to about 1,000 Å; depositing a dielectric layer over at least a portion of the first in situ doped amorphous silicon layer; depositing a second doped amorphous silicon layer over at least a portion of the dielectric layer; and forming a flash memory cell in the flash memory cell area of the substrate and a select gate transistor in the select gate area substrate, the flash memory cell comprising the second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, and the second doped amorphous silicon layer, and the select gate transistor comprising the first oxide layer, second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, and the second doped amorphous silicon layer.

Claims

1. A method of forming a NAND type flash memory device, comprising:

growing a first oxide layer over at least a portion of a substrate, the substrate including a flash memory cell area and a select gate area;

removing a portion of the first oxide layer in the flash memory cell area of the substrate;

growing a second oxide layer over at least a portion of the substrate in the flash memory cell area and over at least a portion of the a first oxide layer in the select gate area;

depositing a first in situ doped amorphous silicon layer over at least a portion of the second oxide layer, the first in situ doped amorphous silicon layer having a thickness from about 400 Å

to about 1,000 Å

;

depositing a dielectric layer over at least a portion of the first in situ doped amorphous silicon layer;

depositing a second doped amorphous silicon layer over at least a portion of the dielectric layer; and

forming a flash memory cell in the flash memory cell area of the substrate and a select gate transistor in the select gate area substrate, the flash memory cell comprising the second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, and the second doped amorphous silicon layer, and the select gate transistor comprising the first oxide layer, second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, and the second doped amorphous silicon layer.

2. The method of claim 1, wherein the first oxide layer has a thickness from about 130 Å

to about 170 Å

.

3. The method of claim 1, wherein the first in situ doped amorphous silicon layer comprises a phosphorus in situ doped amorphous silicon layer.

4. The method of claim 1, wherein the first doped amorphous silicon layer has a thickness from about 600 Å

to about 900 Å

.

5. The method of claim 1, wherein the dielectric layer comprises a first oxide layer, a nitride layer over the first oxide layer, and a second oxide layer over the nitride layer.

6. The method of claim 1, wherein the second oxide layer in the flash memory cell area has a thickness from about 70 Å

to about 110 Å

.

7. The method of claim 1, wherein the first and second oxide layers have a combined thickness from about 150 Å

to about 190 Å

.

8. The method of claim 1, wherein the second doped amorphous silicon layer comprises a phosphorus in situ doped amorphous silicon layer having a thickness from about 1,000 Å

to about 1,400 Å

.

9. A method of forming a flash memory cell and a select gate transistor of a NAND type flash memory device, comprising:

growing a first oxide layer having a thickness from about 130 Å

to about 170 Å

over at least a portion of a substrate, the substrate including a flash memory cell area and a select gate area;

removing a portion of the first oxide layer in the flash memory cell area of the substrate;

growing a second oxide layer over at least a portion of the substrate in the flash memory cell area and over at least a portion of the first oxide layer in the select gate area;

depositing a first in situ doped amorphous silicon layer over at least a portion of the second oxide layer, the first doped amorphous silicon layer having a thickness from about 500 Å

to about 950 Å

;

depositing a dielectric layer over at least a portion of the first in situ doped amorphous silicon layer;

depositing a second doped amorphous silicon layer over at least a portion of the dielectric layer;

depositing a tungsten silicide layer over the second doped amorphous silicon layer using SiH₂Cl₂ and WF₆; and

forming a flash memory cell in the flash memory cell area of the substrate and a select gate transistor in the select gate area substrate, the flash memory cell comprising the second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, the second doped amorphous silicon layer, and the tungsten silicide layer, and the select gate transistor comprising the first oxide layer, the second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, the second doped amorphous silicon layer, and the tungsten silicide layer.

10. The method of claim 9, wherein the first in situ doped amorphous silicon layer is deposited at a temperature from about 490°

C. to about and a pressure from about 350 mTorr to about 600 mTorr.

11. The method of claim 9, wherein the first in situ doped amorphous silicon layer comprises at least one of phosphorus and arsenic.

12. The method of claim 9, wherein the first in situ doped amorphous silicon layer has a dopant concentration from about 1×

10¹⁶ ions/cm³ to about 1×

10²⁰ ions/cm³.

13. The method of claim 9, wherein the dielectric layer has a thickness from about 110 Å

to about 150 Å and

comprises a first oxide layer, a nitride layer over the first oxide layer, and a second oxide layer over the nitride layer.

14. The method of claim 9, wherein the tungsten silicide layer is deposited at a temperature from about 450°

C. to about 650°

C. and a pressure from about 70 Pa to about 120 Pa.

15. The method of claim 9, wherein the tungsten silicide layer is deposited using a gas flow comprising from about 50 sccm to about 250 sccm SiH₂Cl₂ and from about 2 sccm to about 10 sccm WF₆ and optionally from about 100 sccm to about 250 sccm of an inert gas.

16. A method of forming a select gate transistor for a NAND type flash memory device, comprising:

forming a first oxide layer having a thickness from about 130 Å

to about 170 Å

over at least a portion of a substrate;

forming a second oxide layer over the first oxide layer to provide a gate oxide, the gate oxide having a thickness from about 150 Å

to about 190 Å

; and

depositing an in situ doped amorphous silicon layer over the gate oxide at a temperature from about 450°

C. to about 590°

C. under a pressure from about 300 mTorr to about 700 mTorr, the in situ doped amorphous silicon layer having a thickness from about 400 Å

to about 1,000 Å

, and a dopant concentration from about 1×

10¹⁵ ions/cm³ to about 2×

10²⁰ ions/cm³.

17. The method of claim 16, wherein the first oxide layer is formed using a dry oxidation process.

18. The method of claim 16, wherein the gate oxide has a thickness from about 160 Å

to about 180 Å

.

19. The method of claim 16, wherein the in situ doped amorphous silicon layer having a thickness from about 600 Å

to about 900 Å

.

20. The method of claim 16, wherein the in situ doped amorphous silicon layer has a phosphorus dopant concentration is from about 1×

10¹⁷ ions/cm³ to about 5×

10¹⁹ ions/cm³.