Self aligned contact using spacers on the ILD layer sidewalls

• US 6,235,593 B1
• Filed: 02/18/1999
• Issued: 05/22/2001
• Est. Priority Date: 02/18/1999
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Jenn Ming
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): EATON, KURT M
• Application Number:
  US09/252,628
• Time in Patent Office: 824 Days
• Field of Search: 438/199, 438/221, 438/586, 438/595, 438/597, 438/618, 438/639, 438/239, 438/279, 438/299, 438/696, 438/702
• US Class Current: 438/279
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665

Abstract

A method for a self-aligned contact (SAC) that forms top and bottom spacers on the sidewalls of the interlevel dielectric layer. Spaced gate structures are formed between said spaced isolation regions. The gate structure is comprised of a gate oxide layer; a conductive layer; a cap layer. Lightly doped drain regions (LDD) are formed. An interlevel dielectric (ILD) layer is formed. A contact hole is etched that exposes the LDD region between the gate structures and removes a portion of the cap layer. An interlevel dielectric spacer layer is formed over the interlevel dielectric layer, the sidewalls of the contact hole and on the LDD region. In a key step, the interlevel dielectric spacer layer is anisotropically etched forming a top spacer on the sidewalls of the upper opening and a bottom spacer on the lower opening. A contact plug is formed to fill the contact hole and electrically contacting the LDD region. The invention also forms borderless contact hole spacers. The invention'"'"'s IDL spacers can be thinner than conventional spacers and allow better gap filling for the contact plug.

Claims

1. A method of fabrication of a self aligned contact (SAC) using thin interlevel dielectric spacers comprising the steps of:

a) forming spaced isolation regions in a substrate;

said substrate having a self aligned contact area and a borderless contact area;

b) forming a gate dielectric layer on said substrate;

c) forming a conductive layer over said gate dielectric layer;

d) forming a cap layer over said conductive layer;

said cap layer having a bottom;

e) patterning said cap layer, said conductive layer and said gate dielectric layer to form spaced gate structures on said substrate;

implanting ions into said substrate adjacent to said gate structures to form LDD regions in said substrate;

depositing a liner layer over said substrate and said gate structure;

f) forming an interlevel dielectric layer over said substrate and gate structures;

g) etching said interlevel dielectric layer and said cap layer forming a contact hole that exposes said LDD region between said gate structures; and

that removes a section of said liner layer on said cap layer leaving remaining portions of said liner layer, and removes a portion of said cap layer;

said contact hole having sidewalls of said interlevel dielectric layer;

said contact hole have an upper opening above the top of said conductive layer; and

a lower opening below the bottom of said cap layer;

the remaining portion of said liner layer on the sidewalls of said gate structure is a first liner spacer;

h) forming an interlevel dielectric spacer layer over said interlevel dielectric layer, the sidewalls of said contact hole and on said LDD region;

i) anisotropically etching said interlevel dielectric spacer layer forming a top spacer on the sidewalls of said upper opening and a bottom spacer on said lower opening;

said bottom spacer is on said first liner spacer; and

j) forming a contact plug filling said contact hole and electrically contacting said LDD region.

2. The method of claim 1 wherein said conductive layer comprised of a polysilicon layer and an overlying polycide layer.

3. The method of claim 1 wherein said interlevel dielectric spacer layer has a thickness of between about 100 and 500 Å

; and

is composed of silicon oxide, silicon nitride or Silicon oxynitride.

4. The method of claim 1 wherein said top spacer has a height in a range of between about 200 and 1000 Å

and a width of between about 50 and 500 Å and

said bottom spacer has a height in range of between about 2000 and 3000 Å and

a width of between about 50 and 500 Å

; and

said spaced gate structures are spaced between about 0.15 and 0.35 μ

m apart.

5. The method of claim 1 which further includes forming borderless contact spacer on the sidewalls of a borderless contact hole.

6. The method of claim 1 wherein said upper opening having a top diameter at the top surface of said interlevel dielectric layer between about 0.3 and 0.4 μ

m; and

said lower opening has a bottom diameter at the substrate surface between about 0.15 and 0.35 μ

m.

7. A method of fabrication of a self aligned contact using thin top and bottom spacers comprising the steps of:

a) forming spaced isolation regions in a substrate;

said substrate having a self aligned contact (SAC) area;

b) forming a gate dielectric layer on said substrate;

c) forming a conductive layer over said gate dielectric layer;

d) forming a cap layer over said conductive layer;

said cap layer having a bottom;

e) patterning said cap layer, said conductive layer and said gate dielectric layer to form spaced gate structures on said substrate;

said spaced gate structures are spaced between about 0.15 and 0.75 μ

m apart;

f) implanting ions into said substrate adjacent to said gate structures to form LDD regions in said substrate;

g) depositing a liner layer composed of Silicon oxynitride, SiO₂ or silicon nitride, over said substrate and said gate structures;

h) forming an interlevel dielectric layer over said substrate and gate structures;

i) etching said interlevel dielectric layer and said liner layer and said cap layer forming a contact hole that exposes said LDD region between said gate structures, and leaves remaining portions of said liner layer;

the remaining portion of said liner layer on the sidewalls of said gate structure is a first liner spacer; and

removes a portion of said cap layer;

said contact hole having sidewalls of said interlevel dielectric (ILD) layer;

said contact hole have a upper opening above the top of said conductive layer; and

a lower opening below the bottom of said cap layer;

the etch leaving remaining portions of said liner layer;

j) forming an interlevel dielectric spacer layer over said interlevel dielectric layer;

the sidewalls of said contact hole and on said LDD region;

(1) said interlevel dielectric spacer layer has a thickness of between about 100 and 500 Å

; and

is composed of silicon oxide, silicon nitride or Silicon oxynitride (SiON);

k) anisotropically etching said interlevel dielectric spacer layer forming a top spacer on the sidewalls of said upper opening and a bottom spacer on said lower opening;

said bottom spacers formed on the sidewalls of said first liner spacer;

l) forming a contact plug filling said contact hole and electrically contacting said LDD region.

8. The method of claim 7 wherein said upper opening having a top diameter at the top surface of said interlevel dielectric layer between about 0.3 and 0.4 μ

m; and

said lower opening have a bottom diameter at the substrate surface between about 0.15 and 0.35 μ

m.

9. The method of claim 7 wherein said top spacer has a height in a range of between about 200 and 1000 Å

and a width of between about 50 and 500 Å

; and

said bottom spacer has a height in a range of between about 2000 and 3000 Å and

a width of between about 50 and 500 Å

.

10. A method of fabrication of a self aligned contact using thin top and bottom spacers and forming a borderless contact with borderless contact spacers comprising the steps of:

a) forming spaced isolation regions in a substrate;

said substrate having a self aligned contact (SAC) area and a borderless contact area;

b) forming a gate dielectric layer on said substrate;

c) forming a conductive layer over said gate dielectric layer;

d) forming a cap layer over said conductive layer;

said cap layer having a bottom;

e) patterning said cap layer, said conductive layer and said gate dielectric layer to form spaced gate structures on said self aligned contact area;

said spaced gate structures are spaced between about 0.15 and 0.35 μ

m apart;

f) implanting ions into said substrate adjacent to said gate structures to form LDD regions in said substrate;

g) depositing a liner layer composed of silicon nitride, over said substrate and said gate structures;

h) forming an interlevel dielectric layer over said substrate and gate structures;

said interlevel dielectric layer is comprised of silicon oxide;

i) etching said interlevel dielectric layer and said liner layer, a section of said liner layer on said cap layer; and

said cap layer forming a contact hole in said self aligned contact area and a borderless contact hole in said borderless contact area;

said contact hole exposes said LDD region between said gate structures and removes a portion of said cap layer;

said contact hole and said borderless contact hole defined by sidewalls of said interlevel dielectric layer;

the etch is performed using a RIE etch with a F based chemistry with a SiO₂ to silicon nitride selectivity between 5 and 15;

(1) said contact hole have a upper opening above the top of said conductive layer, and a lower opening below the bottom of said cap layer;

(2) said upper opening having a top diameter at the top surface of said interlevel dielectric layer between about 0.3 and 0.4 μ

m; and

said lower opening have a bottom diameter at the substrate surface between about 0.15 and 0.35 μ

m;

(3) the etch leaving remaining portions of said liner layer;

the remaining portion of liner layer on the sidewalls of said gate structure is a first liner spacer;

j) forming an interlevel dielectric spacer layer over said interlevel dielectric layer;

the sidewalls of said borderless contact hole, said contact hole and on said LDD region;

said interlevel dielectric spacer layer has a thickness of between about 100 and 500 Å

; and

said interlevel dielectric spacer layer is composed of SiO₂, silicon nitride or Silicon oxynitride;

k) anisotropically etching said interlevel dielectric spacer layer forming (1) borderless contact spacer on said sidewalls of said borderless contact hole, (2) top spacers on the sidewalls of said upper opening and (3) bottom spacers on said lower opening;

said bottom spacers formed on the sidewalls of said first liner spacer;

said top spacer has a height in a range of between about 200 and 1000 Å and

a width of between about 50 and 500 Å

; and

said bottom spacer has a height in a range of between about 2000 and 3000 Å and

a width of between about 50 and 500 Å

;

l) forming a contact plug filling said contact hole and electrically contacting said LDD region and filling said borderless contact hole.