Method for making tungsten metal plugs in a polymer low-K intermetal dielectric layer using an improved two-step chemical/mechanical polishing process

• US 6,235,633 B1
• Filed: 04/12/1999
• Issued: 05/22/2001
• Est. Priority Date: 04/12/1999
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Jang, Syun-Ming
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): NGUYEN, THANH T
• Application Number:
  US09/290,924
• Time in Patent Office: 771 Days
• Field of Search: 438/675, 438/685, 438/671-673, 438/624, 438/626-629, 438/631, 438/633-634, 438/637-640, 438/643, 438/645, 438/648
• US Class Current: 438/675
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation

Abstract

A novel two-step chem/mech polishing process is described for making tungsten metal plugs in a low-k polymer intermetal dielectric (IMD) layer for ULSI circuits. Since the etch selectivity between the polymer and photoresist is low, a hard mask (SiO₂) is used over the low-k IMD layer to allow contact openings to be etched in the low-k polymer. A tungsten metal is deposited and a first polishing step, having a high polishing selectivity of tungsten to SiO₂, is used to form tungsten plugs. However, during the etching of the contact openings, erosion of the hard mask at the periphery of the openings is damaged and degrades the IMD, and causes residual metal between the plugs to cause intralevel shorts. To eliminate this problem, a second shorter polishing step, having a low polishing selectivity of tungsten to SiO₂, is then used to remove the hard mask and remove any residual metal between adjacent metal plugs.

Claims

1. A method for making metal plugs in an intermetal dielectric layer comprising the steps of:

providing a semiconductor substrate having semiconductor devices and a planar insulating layer on surface of said substrate;

depositing a conducting layer on said planar insulating layer;

patterning said conducting layer to form electrical interconnections for said semiconductor devices;

depositing a planar intermetal dielectric layer over said electrical interconnections;

depositing a hard mask layer on said intermetal dielectric layer;

etching contact openings in said hard mask layer and said intermetal dielectric layer to said electrical interconnections;

depositing a conformal barrier layer on said hard mask layer and in said contact openings;

depositing a metal layer sufficiently thick to fill said contact openings and to form an planar surface;

forming metal plugs in said contact openings by a first chemical/mechanical polishing of said metal layer and said barrier layer selectively to said hard mask;

using a second chemical/mechanical polishing to remove said hard mask layer and polishing said metal plugs at a comparable polishing rate and thereby minimizing electrical shorts between adjacent said metal plugs.

2. The method of claim 1, wherein said conducting layer is a multilayer composed of a lower titanium/titanium nitride layer, an aluminum/copper alloy, and an upper titanium/titanium nitride layer, where said titanium/nitride layers are barrier/adhesion layers.

3. The method of claim 1, wherein said intermetal dielectric layer is a polymer, and has a thickness of between about 7000 and 9000 Angstroms.

4. The method of claim 3, wherein said polymer is a poly(arylene ether).

5. The method of claim 1, wherein said hard mask layer is silicon oxide deposited by plasma-enhanced chemical vapor deposition (PECVD).

6. The method of claim 1, wherein said hard mask layer is deposited to a thickness of between about 1000 and 2000 Angstroms.

7. The method of claim 1, wherein said barrier layer is a multilayer of titanium and titanium nitride and is deposited to a total thickness of between about 200 and 500 Angstroms.

8. The method of claim 1, wherein said metal layer is tungsten and is deposited to a thickness of between about 3500 and 6000 Angstroms.

9. The method of claim 1, wherein said first chemical/mechanical polishing is carried out having a polishing selectivity of metal to PECVD oxide of at least greater than 100:

1.

10. The method of claim 1, wherein said second chemical/mechanical polishing is carried out and has a polishing selectivity of metal to PECVD oxide of at least less than 25:

1.

20. The method of claim 1, wherein said second chemical/mechanical polishing is carried out and has a polishing selectivity of tungsten metal to PECVD oxide of at least less than 25:

1.

11. A method for making metal plugs in an intermetal dielectric layer comprising the steps of:

providing a semiconductor substrate having semiconductor devices and a planar insulating layer on surface of said substrate;

depositing a conducting layer on said planar insulating layer;

patterning said conducting layer to form electrical interconnections for said semiconductor devices;

depositing a planar intermetal dielectric layer composed of polymer over said electrical interconnections;

depositing a hard mask layer on said intermetal dielectric layer;

etching contact openings in said hard mask layer and said intermetal dielectric,layer to said electrical interconnections;

depositing a conformal barrier layer on said hard mask layer and in said contact openings;

depositing a tungsten metal layer sufficiently thick to fill said contact openings and to form an planar surface;

forming tungsten metal plugs in said contact openings by a first chemical/mechanical polishing of said tungsten metal layer and said barrier layer selectively to said hard mask;

using a second chemical/mechanical polishing to remove said hard mask layer and polishing said tungsten metal plugs at a comparable polishing rate and thereby minimizing electrical shorts between adjacent said metal plugs.

12. The method of claim 11, wherein said conducting layer is a multilayer composed of a lower titanium/titanium nitride layer, an aluminum/copper alloy, and an upper titanium/titanium nitride layer, where said titanium/nitride layers are barrier/adhesion layers.

13. The method of claim 11, wherein said intermetal dielectric layer and has a thickness of between about 7000 and 9000 Angstroms.

14. The method of claim 11, wherein said polymer is a poly(arylene ether).

15. The method of claim 11, wherein said hard mask layer is silicon oxide deposited by plasma-enhanced chemical vapor deposition (PECVD).

16. The method of claim 11, wherein said hard mask layer is deposited to a thickness of between about 1000 and 2000 Angstroms.

17. The method of claim 11, wherein said barrier layer is a multilayer of titanium and titanium nitride and is deposited to a total thickness of between about 200 and 500 Angstroms.

18. The method of claim 11, wherein said tungsten metal layer is deposited to a thickness of between about 3500 and 6000 Angstroms.

19. The method of claim 11, wherein said first chemical/mechanical polishing is carried out having a polishing selectivity of tungsten to PECVD oxide of at least greater than 100:

1.