Metallization outside protective overcoat for improved capacitors and inductors

• US 6,236,101 B1
• Filed: 10/30/1998
• Issued: 05/22/2001
• Est. Priority Date: 11/05/1997
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Khatibzadeh, M. Ali, Arch, John Kenneth, Hutter, Louis Nicholas, Erdeljac, John P.
• Primary Examiner(s): Lee, Eddie C.
• Assistant Examiner(s): Ortiz, Edgardo
• Application Number:
  US09/183,821
• Time in Patent Office: 935 Days
• Field of Search: 257/531, 257/532, 257/758, 257/533, 438/238
• US Class Current: 257/531
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A thick layer of copper is formed on the outside the protective overcoat (PO) which protects an integrated circuit, and forms both an inductor and the upper electrode of a capacitor. Placing this layer outside the PO greatly reduces parasitic capacitances with the substrate in the devices.

Claims

1. An integrated circuit device, comprising:

a semiconductor substrate;

a field oxide region formed over a first portion of said semiconductor substrate;

a polysilicon layer formed over and insulated from a second portion of said semiconductor substrate;

a first insulator layer formed over said field oxide region and said polysilicon layer;

a metal layer formed over a portion of said first insulator layer;

a second insulator layer formed over said metal layer and said first insulator layer;

a first metal capacitor plate formed over said second insulator layer and said field oxide region;

a protective overcoat formed over said second insulator layer, an opening in said protective overcoat exposing said first metal capacitor plate;

a capacitor dielectric formed over said first metal capacitor plate; and

a second metal capacitor plate formed over said capacitor dielectric.

2. The integrated circuit device of claim 1, wherein said second insulator layer is spin-on glass.

3. The integrated circuit device of claim 1, wherein said first metal capacitor plate is aluminum.

4. The integrated circuit device of claim 1, wherein said protective overcoat is silicon nitride.

5. The integrated circuit device of claim 1, wherein said capacitor dielectric comprises a layer of nitride formed on said first metal capacitor plate and a layer of titanium tungsten formed on said layer of nitride.

6. The integrated circuit device of claim 1, wherein said second metal capacitor plate is copper.

7. The integrated circuit device of claim 6, wherein said copper is greater than 5 microns thick.

8. The integrated circuit device of claim 6, wherein said copper is in the range of 11-12 microns thick.

9. The integrated circuit device of claim 1, further comprising an inductor formed of metal over said protective overcoat and said field oxide region.

10. The integrated circuit device of claim 1, wherein said capacitor dielectric extends over a portion of said protective overcoat, said second metal capacitor plate extending over said portion of said protective overcoat.