Integrated high-performance decoupling capacitor and heat sink

• US 6,236,103 B1
• Filed: 03/31/1999
• Issued: 05/22/2001
• Est. Priority Date: 03/31/1999
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Voldman, Steven H., Stamper, Anthony K., Bernstein, Kerry, Geffken, Robert M., Pricer, Wilbur D.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Ha, Nathan W.
• Application Number:
  US09/283,828
• Time in Patent Office: 783 Days
• Field of Search: 257/532, 257/533, 257/534, 257/535, 257/537, 438/957, 438/382, 438/665, 438/118
• US Class Current: 257/532
• CPC Class Codes: H01L 23/3672 Foil-like cooling fins or heat sinks being part of lead-frames H01L23/49568
• CPC Class Codes: H01L 23/3735 Laminates or multilayers, e.g. direct bond copper ceramic substrates
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/10158 at the passive surface

Abstract

A significant and very effective decoupling capacitor and heat sink combination that, in a single structure provides both a heat sink and a decoupling capacitor in close proximity to the active circuit on the chip requiring either heat sinking or decoupling capacitance or both. This is achieved by forming on a semiconductor chip, having a buried oxide layer therein, an integrated high-performance decoupling capacitor that uses a metallic deposit greater than 30 microns thick formed on the back surface of the chip and electrically connected to the active chip circuit to result in a significant and very effective decoupling capacitor and heat sink in close proximity to the active circuit on the chip requiring such decoupling capacitance and heat sinking capabilities. The decoupling capacitance can use the substrate of the chip itself as one of the capacitive plates and a formed metallic deposit as the second capacitive plate which also serves as a heat sink for the active circuit formed in the chip. The structure thus provides both a significant and effective decoupling capacitance in close proximity to the active circuit on the chip requiring such decoupling capacitance as well as providing improved heat sinking for the decoupled active circuit.

Claims

1. A semiconductor circuit comprising:

a body having first, second and third regions;

said first region being formed of semiconductor material and having a first and a second major surface;

said third region having a first and a second major surface;

said second region being comprised of a first dielectric layer and positioned on said second major surface of said first region and on said first major surface of said third region so as to lie between and separate said first and third regions;

an integrated circuit, comprised of a plurality of active and passive devices, formed in said first region and a plurality of wiring levels on said first major surface of said first region;

respective ones of said wiring levels being coupled to respective ones of said active and passive devices;

a layer of isolating material on said second major surface of said third region;

a metallic deposit on said layer of isolating material;

first conductive means for connecting a first one of said wiring levels to said first region and second conductive means for connecting a second one of said wiring levels to said metallic deposit on said layer of isolating material whereby said third region forms the first plate of a capacitor with respect to said metallic deposit on said layer of isolating material which forms the second plate of the capacitor and thermally dissipates heat from said integrated circuit.

2. The circuit of claim 1 wherein said first region is formed of silicon and said layer of isolating material is selected from the group consisting of polyamide, silicon nitride, silicon dioxide, tantalum, tantalum nitride, tungsten and tungsten nitride.

3. The circuit of claim 1 wherein said third region is formed of a conductive material and said layer of isolating material is selected comprised of two layers of tantalum separated by a layer of an oxide.

4. The circuit of claim 2 wherein said first and third regions are both formed of silicon and said first region is at least 0.3 microns thick and said second region is at least 20 microns thick.

5. The circuit of claim 4 wherein said second region is formed of silicon dioxide and is at least 500 Å

in thickness, first region is formed of silicon and third region is formed of a refractory layer selected from the group consisting of tantalum, tantalum nitride, tungsten and tungsten nitride coated with a metal selected from the group consisting of copper, gold, lead, aluminum, tin, copper aluminum, titanium, chrome and alloys thereof.

6. A semiconductor circuit comprising:

a substrate comprised of first and second regions;

a dielectric layer interposed between and separating said first and second regions;

said first region being formed of semiconductor material;

an integrated circuit, comprised of a plurality of active and passive devices, formed in said first region, and a plurality of wiring levels on a major surface of said first region;

respective ones of said wiring levels being coupled to respective ones of said active and passive devices;

an isolation layer on a major surface of said second region;

a first metallic deposit on said isolation layer;

a first opening having extended walls passing through said first and second regions, said dielectric layer and said isolation layer from said wiring levels to said metallic deposit on said isolation layer;

a second opening having extended walls passing through said first region and said first dielectric layer from said wiring levels to said second region;

a second dielectric layer on said walls in said first and second openings and first and second conductive deposits respectively in said first and second openings;

a first conductive deposit in said first opening being connected to a first one of said wiring levels and to said second region and a conductive deposit in said second opening being connected to a second one of said wiring levels and to said metallic deposit on said isolation layer whereby said second region forms the first plate of a capacitor with respect to said metallic deposit on said isolation layer which forms the second plate of a capacitor and thermally dissipates heat from said integrated circuit.

7. The circuit of claim 6 wherein said first region is formed of silicon and said first and second dielectric layers are selected from the group consisting of polyamide, silicon nitride, and silicon dioxide.

8. The circuit of claim 6 wherein said first and second regions are both formed of silicon and said first region is at least 0.3 microns thick and said second region is at least 20 microns thick.

9. The circuit of claim 7 wherein said first dielectric is at least 3800 Å

in thickness, said first region is formed of silicon and said second region is selected from the group consisting of tungsten, copper, gold, lead, aluminum, tin, copper aluminum, titanium, chrome and alloys thereof.

10. The circuit of claim 9 wherein said first and second conductive deposits respectively in said first and second vias are selected from the group consisting of polysilicon, copper, gold, lead, aluminum, tin, copper, aluminum, titanium, tungsten, tantalum and alloys of copper, gold, lead, aluminum, tungsten, tantalum and tin.

11. The circuit of claim 6 wherein

said second region has a plurality of grooves therein with each of said grooves is separated from another groove by a fin;

said isolation layer being deposited in said grooves; and

said first metallic deposit being deposited in said grooves and overlying said isolation layer.

12. The circuit of claim 6 wherein

said second region has a plurality of grooves therein wherein each of said grooves is separated from an adjacent groove by a fin;

said isolation layer being deposited in said grooves and over said fins; and

said first metallic deposit being deposited in said grooves and over said fins and overlying said isolation layer.

13. The circuit of claim 6 wherein said substrate is formed of a silicon, said dielectric layers are selected from the group consisting of polyamide, silicon nitride, and silicon dioxide.