High density integrated circuit packaging with chip stacking and via interconnections

• US 6,236,115 B1
• Filed: 07/29/1999
• Issued: 05/22/2001
• Est. Priority Date: 12/27/1995
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Woychik, Charles Gerard, Gaynes, Michael Anthony, Puligandla, Viswanadham, Zalesinski, Jerzy Maria, Emerick, Alan James
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Chambliss, Alonzo
• Application Number:
  US09/362,859
• Time in Patent Office: 663 Days
• Field of Search: 257/686, 257/700, 257/738, 257/774, 257/777, 257/778, 257/780, 257/737, 257/781, 257/786
• US Class Current: 257/774
• CPC Class Codes: H01L 2224/1134 Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06582 Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 Fully indexed content
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/15312 being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/16152 Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Abstract

Chip stacks with decreased conductor length and improved noise immunity are formed by laser drilling of individual chips, such as memory chips, preferably near but within the periphery thereof, and forming conductors therethrough, preferably by metallization or filling with conductive paste which may be stabilized by transient liquid phase (TLP) processes and preferably with or during metallization of conductive pads, possibly including connector patterns on both sides of at least some of the chips in the stack. At least some of the chips in the stack then have electrical and mechanical connections made therebetween, preferably with electroplated solder preforms consistent with TLP processes. The connections may be contained by a layer of resilient material surrounding the connections and which may be formed in-situ. High density circuit packages thus obtained may be mounted on a carrier by surface mount techniques or separable connectors such as a plug and socket arrangement. The carrier may be of the same material as the chip stacks to match coefficients of thermal expansion. High-density circuit packages may also be in the form of removable memory modules in generally planar or prism shaped form similar to a pen or as a thermal conduction module.

Claims

1. A stack of semiconductor chips comprising:

a first chip;

a second chip; and

a first connection which electrically connects said first and second chips,

wherein said first chip and said second chip each include;

(a) a substrate;

(b) a first hole in said substrate;

(c) a first metallization layer disposed along an interior surface of said first hole, said first metallization layer being the only metallization layer formed within said first hole; and

(d) an interconnect layer disposed on a surface of said substrate adjacent said first hole, said interconnect layer being attached to said first metallization layer in said first hole, said first connection contacting the interconnect layer on said first chip to the interconnect layer on said second chip to establish electrical connection between said first and second chips,

wherein said stack further comprises;

a second connection for electrically connecting said first chip and said second chip, and

wherein said first chip and said second chip each include;

another metallization layer disposed in spaced relation to said first metallization layer along a location at a surface of said substrate where a hole is not located, said second connection contacting the another metallization layer of said first chip and the another metallization layer of said second chip to form a pad-to-pad electrical connection between said first and second chips.

2. A stack of semiconductor chips according to claim 1, wherein said first connection is a transient liquid phase (TLP) joint.

3. A stack of semiconductor chips according to claim 1, wherein said second connection is a transient liquid phase (TLP) joint.