Output buffer with independently controllable current mirror legs

• US 6,236,238 B1
• Filed: 05/13/1999
• Issued: 05/22/2001
• Est. Priority Date: 05/13/1999
• Status: Expired due to Term

• Current Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Original Assignee: Honeywell International Inc.
• Inventors: Welch, Jim R., Wentink, Robert S., Tanji, Todd M.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Lam, David
• Application Number:
  US09/311,242
• Time in Patent Office: 740 Days
• Field of Search: 326/86, 326/83, 326/33, 326/81, 326/82, 327/53, 327/108
• US Class Current: 326/83
• CPC Class Codes: H03G 1/0088 using discontinuously variable devices, e.g. switch-operated
• CPC Class Codes: H03K 19/018585 programmable

Abstract

A programmable output buffer with independently controllable current mirror legs is disclosed. The output buffer includes a current mirror that has a reference leg and a number of current mirror legs. The reference leg is biased using a reference current that is relatively independent of the supply voltage. Each of the current mirror legs is coupled to the output terminal of the output buffer, and conducts a current that is proportional to the reference current. This produces an output current that is relatively independent of variations in the supply voltage. To provide a programmable output power level, each of the current mirror legs are separately enabled. By controlling which of the current mirror legs are enabled, the output power of the output buffer can be controlled.

Claims

1. A buffer having a data input terminal and a data output terminal, the buffer receiving a data input signal on the data input terminal, and providing a data output signal on the data output terminal, the buffer comprising:

current mirror means having a reference leg and two or more current mirror legs, selected current mirror legs having an enable terminal, the reference leg being coupled to the data input terminal of the buffer, and the two or more current mirror legs being coupled to the data output terminal of the buffer;

the data input signal providing an input reference current to the reference leg;

each of the current mirror legs providing an output current in the same direction as the other current mirror legs to the data output terminal with a magnitude that is proportional to the input reference current; and

control means coupled to the enable terminals of selected current mirror legs for enabling a first set of the current mirror legs to provide a desired output current to the data output terminal.

2. A buffer according to claim 1, wherein the control means digitally controls the enable terminals of the selected current mirror legs to control which of the current mirror legs are enabled.

3. A buffer according to claim 1, wherein each of two of the current mirror legs draw a different output current from the data output terminal.

4. A buffer according to claim 1, wherein a first current mirror leg and a second current mirror leg each draw a first output current from the data output terminal.

5. A buffer according to claim 4, wherein a third current mirror leg draws a second output current from the data output terminal, wherein the second output current is twice that of the first output current.

6. A buffer according to claim 5, wherein a fourth current mirror leg draws a third output current from the data output terminal, wherein the third output current is twice that of the second output current.

7. A buffer according to claim 2, wherein the reference leg comprises:

a current source having a first terminal and a second terminal, the first terminal being coupled to a supply voltage;

a first transistor having a gate, a source and a drain, the drain of the first transistor is coupled to the second terminal of the current source, to the data input terminal of the buffer through a coupling capacitor, and to the gate of the first transistor; and

a second transistor having a gate, a source and a drain, wherein the drain of the second transistor is coupled to the source of the first transistor, the source of the second transistor is coupled to ground, and the gate of the second transistor is coupled to the supply voltage.

8. A buffer according to claim 7, wherein each of the selected current mirror legs comprise:

a current mirror transistor having a gate, a source and a drain, wherein the drain of the current mirror transistor is coupled to the data output terminal of the buffer, and the gate of the current mirror transistor is coupled to the gate of the first transistor of the reference leg; and

an enable transistor having a gate, a source and a drain, wherein the drain of the enable transistor is coupled to the source of the current mirror transistor, the source of the enable transistor is coupled to ground, and the gate of the enable transistor is coupled to an enable terminal.

9. A buffer according to claim 8, wherein the enable terminal is coupled to the supply voltage.

10. A buffer according to claim 8, wherein the enable terminal is controlled by the control means.

11. A buffer according to claim 8, wherein selected current mirror legs further include a resistor interposed between the drain terminal of the current mirror transistor and the data output terminal.

12. A buffer according to claim 7, wherein selected current mirror legs comprise:

a current mirror transistor having a gate, a source and a drain, wherein the gate of the current mirror transistor is coupled to the gate of the first transistor of the reference leg;

an enable transistor having a gate, a source and a drain, wherein the drain of the enable transistor is coupled to the source of the current mirror transistor, the source of the enable transistor is coupled to ground, and the gate of the current mirror transistor is coupled to an enable terminal; and

a cascode transistor having a gate, a source and a drain, wherein the source of the cascode transistor is coupled to the drain of the current mirror transistor, the drain of the cascode transistor is coupled to the data output terminal, and the gate of the cascode transistor is coupled to the supply voltage.

13. A buffer according to claim 12, wherein selected current mirror legs further include a resistor interposed between the drain terminal of the cascode transistor and the data output terminal.

14. A buffer according to claim 13, wherein the resistor in each of the selected current mirror legs is sized so that the resistance of the resistor times the output current of the corresponding current mirror leg equals a constant value across each of the selected current mirror legs.

15. A buffer according to claim 13, further comprising an ESD diode having an anode and a cathode, wherein the anode is coupled to ground and the cathode is coupled to the data output terminal.

16. A buffer according to claim 13, further comprising a tank coupled to the data output terminal, the tank providing harmonic filtration to the data output signal.

17. A buffer according to claim 16, wherein the tank causes the data output signal to rise above the supply voltage at a selected operating frequency.

18. A buffer according to claim 17, wherein the tank causes the data output signal to peak at about two times the supply voltage at the selected operating frequency.

19. A buffer according to claim 17, wherein the cascode transistor is provided between each current mirror transistor and the data output terminal to absorb at least part of the voltage rise above the supply voltage.

20. A buffer according to claim 17, wherein the enable transistor and the current mirror transistor have a gate oxide of a first thickness, and the cascode transistor has a gate oxide of a second thickness, wherein the second thickness is greater than the first thickness.

21. A buffer according to claim 20, wherein the second thickness is about twice as thick as the first thickness.

22. A buffer according to claim 21, wherein the cascode transistor is formed using a dual oxide process and the control transistor and the current mirror transistor are formed using a standard single oxide process.

23. A buffer having an output terminal and powered by a supply voltage, the output terminal of the buffer coupled to a load, wherein the load causes the voltage at the output terminal to exceeding the supply voltage at a selected frequency, the buffer comprising:

drive means for providing a drive current to the output terminal of the buffer, and ultimately to the load; and

a cascode transistor positioned between the drive means and the output terminal for absorbing at least part of the voltage rise of the output terminal above the supply voltage.

24. A buffer according to claim 23, wherein the cascode transistor includes a dual oxide layer while the drive means is formed using a standard single oxide layer.

25. A buffer according to claim 23, wherein the drive means comprises an N-channel FET transistor.

26. A buffer according to claim 23, wherein the drive means comprises a current mirror leg from a current mirror circuit.

27. A buffer according to claim 23, wherein the drive means comprises two stacked N-channel transistors.

28. A method for buffering a data input signal and for providing a data output signal, comprising:

receiving the data input signal;

converting the data input signal to an input reference current;

mirroring the input reference current to two or more current mirror legs, wherein each of the current mirror legs provides an output current in the same direction as the other current mirror legs to the data output signal with a magnitude that is proportional to the input reference current; and

enabling a first set of the current mirror legs to achieve a first output power level in the data output signal.

29. A method according to claim 28, further comprising the step of:

enabling a second set of the current mirror legs to achieve a second output power level in the data output signal, wherein the first output power level is different from the second output power level.