Power-on reset circuit for a high density integrated circuit

• US 6,236,249 B1
• Filed: 06/14/1999
• Issued: 05/22/2001
• Est. Priority Date: 06/12/1998
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Choi, Soo-Hwan, Park, Jong-Mia
• Primary Examiner(s): Wells, Kenneth B.
• Assistant Examiner(s): Luu, An T.
• Application Number:
  US09/333,195
• Time in Patent Office: 708 Days
• Field of Search: 327/142, 327/143, 327/198, 327/146, 327/540, 327/541
• US Class Current: 327/143
• CPC Class Codes: H03K 17/223 in field-effect transistor switches
• CPC Class Codes: H03K 17/284 in field effect transistor switches
• CPC Class Codes: H03K 2217/0036 Means reducing energy consumption

Abstract

A power-on reset circuit reduces power consumption and layout area by utilizing a time delay to deactivate a reset circuit and clamp a reset signal a period of time after a power supply voltage has reached a predetermined level. The reset circuit includes a reset signal generator which maintains the reset signal in an active state until the power supply voltage has reached the predetermined level. The reset signal generator then deactivates the reset signal which causes a delay circuit to begin a time delay after which a delay signal is asserted. The delay signal deactivates a comparator in the reference voltage generator, a voltage detector, and a reset signal generator within the reset circuit, thereby reducing power consumption. The delay signal also activates a clamp circuit which clamps the reset signal to an inactive state.

Claims

1. A power-on reset circuit for an integrated circuit comprising:

a reset circuit for generating a reset signal at a first logic state until a power supply voltage has reached a predetermined level; and

a delay circuit coupled to the reset circuit for generating a delay signal responsive to the reset signal;

wherein the reset circuit generates the reset signal at a second logic state in response to the delay signal;

wherein said reset circuit comprises;

a reference signal generator for generating a reference signal;

a voltage detector coupled to the reference signal generator for generating a start-up signal responsive to the power supply voltage; and

a reset signal generator coupled to the reference signal generator and the voltage detector for generating the reset signal in response to the reference signal and the start-up signal; and

wherein said reset signal generator comprises;

a differential comparator for generating the reset signal at the first logic state while the start-up signal is lower than or equal to the reference signal; and

a clamp circuit coupled to the differential comparator for clamping the reset signal to the second logic state in response to the delay signal.

2. A power-on reset circuit for an integrated circuit comprising:

a reference voltage generator coupled between first and second power supply terminals for generating a reference voltage;

a voltage detector coupled between the first and second power supply terminals for generating a start-up voltage proportional to the voltage at the first power supply terminal;

a reset signal generator coupled to the reference voltage generator and the voltage detector for generating a reset signal in response to the reference voltage and the start-up voltage, the reset signal being maintained in a first logic state until the first power supply voltage has reached a predetermined level; and

a delay circuit for generating a delay signal responsive to the reset signal;

wherein the reset signal generator is deactivated in response to the delay signal such that the reset signal is maintained in a second logic state;

wherein said reference voltage generator comprises;

first through third resistors; and

first through third transistors, each having a controlling electrode and a pair of controlled electrodes; and

wherein the first resistor is coupled between the first power supply terminal and a first node, the second resistor is coupled between the first node and a second node which provides the reference voltage, the controlled electrodes of the first transistor are coupled between the second and a third node, the third resistor is coupled between the third node and a fourth node, the controlled electrodes of the second transistor are coupled between the fourth node and the second power supply terminal, the controlled electrodes of the third transistor are coupled between the first and fourth nodes, the controlling gate of the first transistor is coupled to the first node, the controlling gate of the second transistor is coupled to receive the delay signal, and the controlling gate of the third transistor is coupled to the third node, respectively.

3. A power-on reset circuit for an integrated circuit comprising:

a reference voltage generator coupled between first and second power supply terminals for generating a reference voltage;

a voltage detector coupled between the first and second power supply terminals for generating a start-up voltage proportional to the voltage at the first power supply terminal;

a reset signal generator coupled to the reference voltage generator and the voltage detector for generating a reset signal in response to the reference voltage and the start-up voltage, the reset signal being maintained in a first logic state until the first power supply voltage has reached a predetermined level; and

a delay circuit for generating a delay signal responsive to the reset signal;

wherein the reset signal generator is deactivated in response to the delay signal such that the reset signal is maintained in a second logic state;

wherein said voltage detector comprises;

first and second resistors; and

a transistor having a controlling electrode and a pair of controlled electrodes; and

wherein the first resistor is coupled between the first power supply terminal and a node which provides the start-up voltage, the second resistor and the controlled electrodes of the transistor are serially coupled between the node and the second power supply terminal, and the controlling electrode of the transistor is coupled to receive the delay signal.

4. A power-on reset circuit or an integrated circuit comprising:

a reference voltage generator coupled between first and second power supply terminals for generating a reference voltage;

a voltage detector coupled between the first and second power supply terminals for generating a start-up voltage proportional to the voltage at the first power supply terminal;

a reset signal generator coupled to the reference voltage generator and the voltage detector for generating a reset signal in response to the reference voltage and the start-up voltage, the reset signal being maintained in a first logic state until the first power supply voltage has reached a predetermined level; and

a delay circuit for generating a delay signal responsive to the reset signal;

wherein the reset signal generator is deactivated in response to the delay signal such that the reset signal is maintained in a second logic state;

wherein said reset signal generator comprises;

a differential comparator having a first input terminal for receiving the start-up voltage, a second input terminal for receiving the reference voltage, and an output terminal for generating the reset signal, wherein the differential comparator generates the reset signal at the first logic state while the start-up voltage is lower than or equal to the reference voltage; and

a clamp circuit coupled to the output terminal of the differential comparator for clamping the reset signal to the second logic state in response to the delay signal.

5. A method for generating a reset signal for an integrated circuit comprising:

maintaining the reset signal at a first logic state until a power supply voltage reaches a predetermined level;

switching the reset signal to a second logic state when the power supply voltage has reached the predetermined level;

delaying the reset signal for a period of time after the supply voltage reaches the predetermined level;

clamping the reset signal to the second logic state after the time delay; and

deactivating a comparator after the time delay.

6. A method for generating a reset signal for an integrated circuit comprising:

maintaining the reset signal at a first logic state until a power supply voltage reaches a predetermined level;

switching the reset signal to a second logic state when the power supply voltage has reached the predetermined level;

delaying the reset signal for a period of time after the supply voltage reaches the predetermined level;

clamping the reset signal to the second logic state after the time delay; and

deactivating a reference signal generator after the time delay.

7. A method for generating a reset signal for an integrated circuit comprising:

maintaining the reset signal at a first logic state until a power supply voltage reaches a predetermined level;

switching the reset signal to a second logic state when the power supply voltage has reached the predetermined level;

delaying the reset signal for a period of time after the supply voltage reaches the predetermined level;

clamping the reset signal to the second logic state after the time delay; and

deactivating a voltage detector after the time delay.

8. A method for generating a reset signal for an integrated circuit comprising:

maintaining the reset signal at a first logic state until a power supply voltage reaches a predetermined level;

switching the reset signal to a second logic state when the power supply voltage has reached the predetermined level;

delaying for a period of time after the supply voltage reaches the predetermined level; and

clamping the reset signal to the second logic state after the time delay;

wherein delaying for a period of time includes generating a delay signal responsive to the reset signal; and

wherein the reference signal is generated by a reference signal generator having a comparator, and further including deactivating the comparator responsive to the reset signal after the time delay.

9. A method as set forth in claim 8 wherein the comparator generates the reset signal responsive to a reference signal from a reference signal generator and a start-up signal from a voltage detector, and further including deactivating the reference signal generator and the voltage detector responsive to the reset signal after the time delay.

10. A method as set forth in claim 8 wherein the reset signal is clamped by a clamp circuit, and further including activating the clamp circuit responsive to the reset signal after the time delay.