Operational amplifier circuit including folded cascode circuit

• US 6,236,270 B1
• Filed: 12/15/1999
• Issued: 05/22/2001
• Est. Priority Date: 12/16/1998
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Takeuchi, Junichi
• Primary Examiner(s): Mottola, Steven J.
• Application Number:
  US09/460,980
• Time in Patent Office: 524 Days
• Field of Search: 330/252, 330/253, 330/255, 330/257
• US Class Current: 330/253
• CPC Class Codes: H03F 2203/45301 there are multiple cascaded folded or not folded common gate stages of a cascode dif amp
• CPC Class Codes: H03F 2203/45398 the AAC comprising a voltage generating circuit as bias circuit for the AAC
• CPC Class Codes: H03F 3/3023 with asymmetrical driving of the end stage
• CPC Class Codes: H03F 3/45192 Folded cascode stages

Abstract

The operational amplifier circuit of the present invention includes a first pair of NMOS which receives a first and a second input voltages to respective gate electrodes and has the source electrodes connected in common, a first pair of PMOS whose gate electrodes are connected in common and whose respective source electrodes are connected to respective drain electrodes of the first pair of NMOSs, a second pair of NMOSs whose gate electrodes are connected in common, whose respective source electrodes are connected to respective drain electrodes of the first PMOS, and whose drain electrodes are connected to a current mirror composed of a second pair of PMOS which is based on the first power supply voltage, and another PMOS whose gate electrode is connected to the drain electrode of one of the second pair of NMOS transistor, whose source electrode receives the first power supply voltage, and whose drain electrode is connected to a constant current source composed of another NMOS transistor whose one end is connected to the second power supply voltage.

Claims

1. An operational amplifier circuit comprising:

a first transistor of a first conductivity type having a first control gate supplied with a first input voltage and a first current path coupled between a first node and a second node;

a second transistor of said first conductivity type having a second control gate supplied with a second input voltage and a second current path coupled between said first node and a third node;

a third transistor of a second conductivity type having a third control gate and a third current path coupled between said third node and a fourth node;

a fourth transistor of said second conductivity type having a fourth control gate coupled to said third control gate and a fourth current path coupled between said second node and a fifth node;

a fifth transistor of said first conductivity type having a fifth control gate and a fifth current path coupled between said fourth node and a sixth node;

a sixth transistor of said first conductive type having a sixth control gate coupled to said fifth control gate and having a sixth current path coupled between said fifth node and seventh node;

a current mirror circuit having an input node coupled to said sixth node and an output node coupled to said seventh node; and

a seventh transistor of said second conductive type having a seventh control gate coupled to said seventh node.

2. The amplifier circuit as claimed in claim 1, said amplifier circuit further comprising:

a first constant current source coupled between said first node and a first power source line.

3. The amplifier circuit as claimed in claim 1, said amplifier circuit further comprising:

a second constant current source coupled between said third node and a second power source line; and

a third constant current source coupled between said second node and said second power source line.

4. The amplifier circuit as claimed in claim 3, wherein a current flowing in said second constant current source is substantially equal to a current flowing in said third constant current source.

5. The amplifier circuit as claimed in claim 1, said amplifier circuit further comprising:

a fourth constant current source coupled between said fourth node and a first power source line; and

a fifth constant current source coupled between said fifth node and said first power source line.

6. The amplifier circuit as claimed in claim 5, wherein a current flowing in said fourth constant current source is substantially equal to a current flowing in said fifth constant current source.

7. The amplifier circuit as claimed in claim 1, wherein said third and fourth control gates are supplied with a first constant voltage and said fifth and sixth control gates are supplied with a second constant voltage.

8. The amplifier circuit as claimed in claim 1, said amplifier circuit further comprising a sixth constant current source coupled between a first power source line and an output node, wherein said seventh transistor has a seventh current path coupled between said output node and a second power source line.

9. The amplifier circuit as claimed in claim 1, wherein said first, second, fifth, and sixth transistors are N-channel MOS transistors, and said third, fourth, and seventh transistors are P-channel MOS transistors.

10. The amplifier circuit as claimed in claim 1, wherein said first, second, fifth, and sixth transistors are NPN transistors, and said third, fourth, and seventh transistors are PNP transistors.

11. An operational amplifier circuit comprising:

a first transistor of a first conductivity type having a first control gate supplied with a first input voltage and a first current path coupled between a first node and a second node;

a second transistor of said first conductivity type having a second control gate supplied with a second input voltage and a second current path coupled between said first node and a third node;

a third transistor of a second conductivity type having a third control gate supplied with a first constant voltage and a third current path coupled between said third node and a fourth node;

a fourth transistor of said second conductivity type having a fourth control gate supplied with said first constant voltage coupled to said third control gate and a fourth current path coupled between said second node and a fifth node;

a fifth transistor of said first conductivity type having a fifth control gate supplied with a second constant voltage and a fifth current path coupled between said fourth node and a sixth node;

a sixth transistor of said first conductive type having a sixth control gate supplied with a second constant voltage coupled to said fifth control gate and having a sixth current path coupled between said fifth node and seventh node;

a current mirror circuit having an input node coupled to said sixth node and an output node coupled to said seventh node;

a seventh transistor of said second conductive type having a seventh control gate coupled to said seventh node;

a first constant current source coupled between said first node and a first power source line;

a second constant current source coupled between said third node and a second power source line;

a third constant current source coupled between said second node and said second power source line;

a fourth constant current source coupled between said fourth node and said first power source line;

a fifth constant current source coupled between said fifth node and said first power source line; and

a sixth constant current source coupled between said first power source line and an output node;

wherein said seventh transistor has a seventh current path coupled between said output node and said second power source line.

12. The amplifier circuit as claimed in claim 11, wherein a current flowing in said second constant current source is substantially equal to a current flowing in said third constant current source.

13. The amplifier circuit as claimed in claim 12, wherein a current flowing in said fourth constant current source is substantially equal to a current flowing in said fifth constant current source.

14. An amplifier circuit comprising:

an input circuit receiving a first input signal and a second input signal;

a first folded cascode connected transistor pair coupled to said input circuit;

a second folded cascode connected transistor pair coupled to said first folded cascode connected transistor pair so that said input circuit, said first folded cascode connected transistor pair and said second folded cascode connected transistor pair are connected in series; and

an output circuit coupled to said second folded cascode connected transistor pair to output an output signal.

15. The amplifier circuit as claimed in claim 14, wherein said input circuit includes a first transistor of a first conductive type receiving said first input signal and a second transistor of said first conductive type receiving said second input signal.

16. The amplifier circuit as claimed in claim 15, wherein said first folded cascode connected transistor pair includes a third transistor of a second conductive type coupled to said second transistor and a fourth transistor of said second conductive type coupled to said first transistor.

17. The amplifier circuit as claimed in claim 16, wherein said second folded cascode connected transistor pair includes a fifth transistor of said first conductive type coupled to said third transistor and a sixth transistor of said first conductive type coupled to said fourth transistor.

18. The amplifier circuit as claimed in claim 17, wherein said output circuit includes a seventh transistor of said second conductive type having a control gate coupled to said sixth transistor to output said output signal.

19. The amplifier circuit as claimed in claim 18, wherein said first, second, fifth, and sixth transistors are N-channel MOS transistors, and said third, fourth, and seventh transistors are P-channel MOS transistors.

20. The amplifier circuit as claimed in claim 18, wherein said first, second, fifth, and sixth transistors are NPN transistors, and said third, fourth, and seventh transistors are PNP transistors.