Digital frequency synthesis by sequential fraction approximations

• US 6,236,275 B1
• Filed: 10/24/1997
• Issued: 05/22/2001
• Est. Priority Date: 10/24/1997
• Status: Expired due to Term

• Current Assignee: Ericsson, Inc. (Telefonaktiebolaget LM Ericsson)
• Original Assignee: Ericsson, Inc. (Telefonaktiebolaget LM Ericsson)
• Inventors: Dent, Paul W.
• Primary Examiner(s): KINKEAD, ARNOLD M
• Application Number:
  US08/957,173
• Time in Patent Office: 1,306 Days
• Field of Search: 331/1.A, 331/17, 331/18, 331/16, 375/376, 327/106, 327/107, 327/156, 327/157, 327/159, 327/162
• US Class Current: 331/1.00A
• CPC Class Codes: H03L 7/0898 the source or sink current values being variable H03L7/0896 takes precedence

Abstract

A fractional synthesis approach and arrangement are presented which achieve fine frequency resolution with low phase noise while at the same time retaining a high phase comparison frequency/fast frequency changing speed. An output signal having a desired output frequency is generated by a voltage controlled oscillator (VCO). An output divider divides the output frequency by an output divisor N to produce an output pulse train. The output divisor N may be equal to an output integer N or the output integer plus one N+1, for example, and may change during the generation of a single output frequency. For different desired output frequencies, the value of the output integer N may be varied. A reference divider divides a reference frequency by a reference divisor M to produce a reference pulse train. The reference divisor M may be equal to a reference integer M or the reference integer plus one M+1, for example, and may change during the generation of a single output frequency. A fractional controller may vary the value of the divisor M between successive pulses from the reference divider to produce a mean output pulse frequency having a non-integral relationship to the reference frequency. A phase error detector compares the pulse trains and generates a phase error signal. This signal, which may be filtered or other wise processed, controls the VCO to produce the output signal at the desired output frequency.

Claims

1. A frequency synthesizer for generating an output signal having a desired output frequency comprising:

a reference frequency source for generating a reference signal having a reference frequency;

a reference divider circuit for dividing the reference signal by a reference divisor M to produce a reference pulse train and for varying the reference divisor M in a predetermined pattern in response to an overflow signal during generation of the desired output frequency;

an overflow accumulator connected to the output of the reference divider circuit incremented by pulses output from the reference divider circuit, wherein said overflow accumulator generates said overflow signal when the value of the overflow accumulator reaches a predetermined limit; and

an output signal circuit for generating the output signal having the desired output frequency based on the reference pulse train.

2. The frequency synthesizer as recited in claim 1 wherein the reference divisor M is varied between pulses of the reference pulse train to produce a mean pulse frequency for the reference pulse train having a non-integral relationship to the reference frequency.

3. The frequency synthesizer as recited in claim 1 wherein the output signal circuit comprises:

an oscillator for generating the output signal at the desired output frequency in response to an output control signal; and

an output divider circuit for dividing the output frequency by an output divisor N to produce an output pulse train and comparing the output pulse train the reference pulse train and for generating the output control signal based on the comparison.

4. The frequency synthesizer as recited in claim 3 wherein the output divider circuit comprises:

a phase error detector for comparing the output pulse train and the reference pulse train to produce a phase error signal; and

a signal processor for processing the phase error signal to produce the output control signal.

5. The frequency synthesizer as recited in claim 4, wherein the signal processor comprises a low-pass loop filter.

6. The frequency synthesizer of claim 4, wherein the signal processor includes a a ripple compensation circuit to compensate for the undesired variations of the reference divisor M.

7. The frequency synthesizer of claim 1, wherein the reference divider circuit varies the reference divisor M between a first preselected integer value and a second preselected integer value in a determined pattern, and further wherein the first and second preselected integer values differ by one.

8. A frequency synthesizer for generating an output signal of a desired output frequency comprising:

a reference frequency source for generating a reference signal having a reference frequency;

a reference divider circuit for dividing the reference signal by a reference divisor M and for producing a reference pulse train based on the divided reference signal;

an output divider for dividing the output signal by an output divisor N and for producing an output pulse train based on the divided output signal;

a fractional controller for varying values of the reference divisor M and the output divisor N between a first pair of values (N1, M1) and a second pair of values (N2, M2);

a phase error detector for comparing the reference pulse train and the output pulse train to produce a phase error signal;

a ripple compensator connected to the phase error detector and controlled by the fractional controller to compensate for periodic phase error in the phase error signal; and

a signal processor for processing the phase error signal to produce an output control signal; and

an oscillator for producing the output signal at the desired output frequency in response to the output control signal.

9. The frequency synthesizer of claim 8, wherein the signal processor includes a low-pass loop filter.

10. The frequency synthesizer as recited in claim 8, wherein the fractional controller varies the values of the reference divisor M and the output divisor N between the first and second pairs of values (N1, M1) and (N2, M2) in a determined pattern.

11. The frequency synthesizer of claim 8, wherein said first and second pairs of values define first and second ratios, and wherein the signal processor generates a ripple compensation signal in response to undesired variations of the first and second ratios, and further comprises:

a ripple compensation circuit for combining the phase error signal and the ripple compensation signal to compensate for the undesired variations of the first and second ratios.

12. The frequency synthesizer as recited in claim 11, wherein the ripple compensation signal minimizes any undesired effect of variances in the values of the output or reference divisors N or is M.

13. The frequency synthesizer as recited in claim 8, wherein the ripple compensator minimizes an integral of the periodic phase error.

14. The frequency synthesizer as recited in claim 8, wherein the ripple compensator overcompensates for the periodic phase error.

15. The frequency synthesizer as recited in claim 8, wherein the fractional controller generates a loop gain compensation signal for controlling scaling of the phase error signal generated by the phase error detector.

16. The frequency synthesizer of claim 8, wherein the phase error signal is scaled to minimize variances in the phase error signal.

17. The frequency synthesizer of claim 8, wherein the phase error signal is scaled to minimize periodic variations in the phase error signal caused by varying the values of the output divisor N or the reference divisor M.

18. The frequency synthesizer of claim 8, wherein the phase error signal is scaled based on a current value of either the reference or output divisor M or N.

19. The frequency synthesizer as recited in claim 8, wherein the phase error signal is scaled so that a larger value of the reference divisor M results in a larger correction of the phase error signal.

20. The frequency synthesizer of claim 15, wherein the phase error detector comprises a charge pump phase detector including a pull-up current mirror and a pull-down current mirror for reflecting a current based on the loop gain compensation signal and for generating a negative or positive pulse of current based on a sign of the phase error signal.

21. The frequency synthesizer of claim 20, wherein a width of the pulse of current is based on a magnitude of the phase error signal.

22. The frequency synthesizer of claim 20, wherein a magnitude of the pulse of current is based on the current values of the output and reference divisors N and M.

23. A method for synthesizing a range of desired output frequencies generated by an oscillator which is controlled by a control signal, the method comprising the steps of:

selecting a desired output frequency to be generated by the oscillator;

determining a sequence of integer values that approximates a non-integral factor of a reference frequency;

dividing the reference frequency by the determined sequence of integer values;

accumulating a fractional remainder from the dividing step to control when each of the integer values in the determined sequence is employed in the dividing step;

comparing the divided reference frequency and a signal corresponding to the desired output frequency;

producing an error signal based on the comparison;

processing the error signal to compensate for ripple error in the error signal; and

producing a control signal based on the error signal for controlling the oscillator to produce an output signal having the desired output frequency.

24. The method as recited in claim 23, wherein the integer values are comprised of two integers corresponding to a reference integer M and the reference integer plus ones (M+1).

25. The method as recited in claim 23 further comprising the step of dividing the output signal by an output integer N.

26. The method as recited in claim 25, wherein the value of the output integer N is fixed for a period of time that the desired output frequency is to be generated by the oscillator.

27. The method as recited in claim 25, wherein the value of the output integer N varies in accordance with a predetermined sequence of integers.

28. A method for synthesizing a range of output frequencies generated by an oscillator, comprising the steps of:

selecting a desired output frequency;

dividing a reference frequency by a reference divisor M to generate a reference pulse train;

comparing the reference pulse train to an output pulse train to generate a phase error signal;

processing the phase error signal to produce a control signal for controlling the output frequency of the oscillator;

dividing the output frequency by an output divisor N to obtain said output pulse train;

determining a first pair of integers (N1, M1) having a first ratio therebetween and a second pair of integers (N2, M2) having a second ratio therebetween, said second ratio different from said first ratio; and

periodically alternating said reference divisor M and said output divisor N between said first pair of integer-values (N1, M1) and said second pair of integer values (N2, M2) during generation of the desired output frequency.

29. The method as recited in claim 28, wherein the determining step comprises the step of:

determining a sequence of the first and second pairs of integers (N1, M1) and (N2, M2) which approximates a non-integral factor by which the desired output frequency is related to the reference frequency.

30. The method as recited in claim 29, further comprising the step of:

determining an optimum sequence of the first pair of integers (N1, M1) and the second pair of integers (N2, M2).

31. The method as recited in claim 30, comprising the steps of:

detecting a phase error based on the step of comparing the divided reference frequency and the divided output frequency;

accumulating the phase error; and

determining the values of the first and second pairs of integers (N1, M1) and (N2, M2) and the optimum sequence to reduce the accumulated phase error.

32. The method as recited in claim 28, wherein the step of determining a first pair of integers (N1, M1) and a second pair of integers (N2, M2) comprises the step of determining the values of the first and second pairs of integers (N1, M1) and (N2, M2) in accordance with the following equations:

33. The method as recited in claim 28, further comprising the step of accumulating fractional * remainders from the dividing step to control the timing of when each of the first and second pairs of integers is employed in the dividing step.

34. The method as recited in claim 33, further comprising the step of compensating the control signal for the accumulated fractional remainder.

35. The method as recited in claim 28, wherein the step of dividing generates a ripple error in the phase error signal, and

the method further comprises the step of compensating the control signal for the ripple error.

36. The method as recited in claim 28, wherein the determining step comprises the steps of:

iteratively determining a phase error for selected ones of the pairs of integers;

determining a phase error for each iteration;

determining an integral of the phase error; and

selecting a pair of integers having a minimal integrated phase error.

37. The method as recited in claim 28, wherein the step of determining a first pair of integers vcomprises the step of determining values of the integers M1 and M2 for a minimum phase comparison rate.

38. The method as recited in claim 28, wherein the step of determining a first pair of integers comprises the step of determining values of the integers N1 and N2 for a minimum fractional ripple.

39. The method as recited in claim 28, further comprising the step of generating a gain compensation signal for controlling a gain of the phase error signal.

40. The method as recited in claim 39, wherein the gain compensation signal minimizes any undesired effect of varying the integers N or M.

41. The method as recited in claim 28, further comprising the step of:

scaling the phase error signal to minimize variances in the output frequency.

42. The method in claim 41, wherein the phase error signal is scaled based on a current value of the integers M or N.

43. The method as recited in claim 42, wherein the phase error signal is scaled so that a larger value of the integer M results in a larger magnitude of the phase error signal.

44. The method as recited in claim 28, wherein the determining step comprises the steps of

determining a closest Nth cycle of the output frequency to an Mth cycle of the reference frequency as a function of the values of the reference divisor M, the output frequency, the reference frequency, and an expected phase error;

determining a cumulative expected phase error at the Mth cycle of reference frequency as a function of the values of the reference divisor M, the output frequency, the reference frequency, and the expected phase error, and

determining the values of the reference divisor M and output divisor N that result in a minimum expected phase error.

45. A frequency synthesizer for generating an output signal of a selected one of a plurality of output frequencies, comprising:

a voltage controlled oscillator (VCO) for producing the output signal;

an output divider for selecting an output divisor N being based on the selected one of the output frequencies and being constant during generation of the selected one of the output frequencies, for dividing the output signal by the output divisor N and for generating an output pulse train based on the division of the output signal;

a reference divider for dividing a reference signal at a reference frequency by a reference divisor M, the reference divisor M being varied between two or more integer values on successive division cycles during generation of the selected one of the output frequencies in a predetermined pattern; and

a phase error detector for generating a phase error signal for continuously adjusting the output frequency of the VCO based on the output pulse train and a reference pulse train, wherein the phase error signal is further reduced by combining the phase error signal with a similar but opposing signal which is computed from a ratio of the selected one of the desired output frequencies F_VCO to the reference frequency F_ref to satisfy the equation, $\frac{A<br><br>\text{\hspace{1em}<br><br>}<br><br>1*M<br><br>\text{\hspace{1em}<br><br>}<br><br>1+A<br><br>\text{\hspace{1em}<br><br>}<br><br>2*M<br><br>\text{\hspace{1em}<br><br>}<br><br>2+.\text{\hspace{1em}<br><br>}.\text{\hspace{1em}<br><br>}.\text{\hspace{1em}<br><br>}<br><br>+\mathrm{Ai}*\mathrm{Mi}}{N*\left(A<br><br>\text{\hspace{1em}<br><br>}<br><br>1+A<br><br>\text{\hspace{1em}<br><br>}<br><br>2+.\text{\hspace{1em}<br><br>}.\text{\hspace{1em}<br><br>}.\text{\hspace{1em}<br><br>}<br><br>+\mathrm{Ai}\right)}=\frac{F_{\mathrm{ref}}}{F_{\mathrm{VCO}}}$

 

where M1, M2 . . . Mi represent i different values for the reference divisor M used by the reference divider during production of the selected one of the output frequencies F_VCO and A1, A2 . . . Ai represent a corresponding number of times that each value of the reference divisor M is used in one cycle of the predetermined pattern.

46. The frequency synthesizer as recited in claim 45, wherein the predetermined pattern is predetermined to reduce undesired spectral components of the phase error signal generated by the phase comparator.

53. A frequency synthesizer as recited in claim 45, wherein the value of the output divisor N is selected for each selected one of the output frequencies to obtain an optimal ripple error.

47. A frequency synthesizer for generating an output signal of a selected one of a plurality of output frequencies F_VCO, comprising:

a voltage controlled oscillator (VCO) for producing the output signal;

an output divider for selecting an output divisor N being based on the selected one of the output frequencies and being constant during generation of the selected one of the output frequencies, for dividing the output signal by the output divisor N and for generating an output pulse train based on the division of the output signal;

a reference divider for dividing a reference signal at a reference frequency F_REF by a reference divisor M, and for generating a reference pulse train based on the division of the reference signal, the reference divisor M being varied between two or more integer values on successive division cycles during generation of the selected one of the output frequencies in a predetermined pattern;

a modulo-Q accumulator based on an integer Q and being modulo-Q incremented or decremented on each count cycle of the reference and output dividers by an integer X, and wherein, the value of the reference divisor M used on the particular one of the successive division cycles is a reference integer M or the reference integer plus one (M+1) based whether the modulo-Q accumulator overflows or underflows on a last accumulation cycle; and

a phase error detector for generating a phase error signal for continuously adjusting the output frequency F_VCO of the VCO based on the output pulse train and the reference pulse train.

48. The frequency synthesizer as recited in claim 47, wherein the phase error detector compares phases of the reference pulse train and the output pulse train, and wherein the value of the reference divisor M is selected based on a desired frequency of phase comparisons.

49. The frequency synthesizer as recited in claim 48, wherein the output divisor N is determined in accordance with the following equation:

50. The frequency synthesizer as recited in claim 47, wherein the integer Q is determined in accordance with the following:

51. The frequency synthesizer as recited in claim 50, wherein the common factor C is a highest common factor of the selected one of the output frequencies F_vco and the reference frequency F_ref.

52. The frequency synthesizer as recited in claim 47, wherein the integer X is determined in accordance with the following equation:

54. A frequency synthesizer comprising:

a voltage controlled oscillator (VCO) for generating an output signal at an output frequency;

an output divider for dividing the output frequency by an output integer N to produce an output pulse train;

a reference divider for dividing a reference frequency by a reference integer M to produce a reference pulse train;

a phase comparator for comparing the reference and output pulse trains, for generating a phase error signal based on the comparison and for controlling the VCO to produce a desired output frequency based on the phase error signal; and

a controller for varying the output integer N and the reference integer M on successive division cycles of the output divider or the reference divider between two pairs of integers (N1, M1) and (N2, M2) calculated such that N1*F_ref/M1 and N2 *F_ref/M2, where F_ref is the reference frequency, are best approximations, respectively, of frequencies less than and greater than the desired output frequency.

55. The frequency synthesizer as recited in claim 54, wherein the values of the output and reference integers N and M are alternated between the two pairs of integers (N1, M1) and (N2, M2) in a cyclic pattern which minimized deviation of phase of the output signal from an ideal phase of the output signal at the desired output frequency.

56. A frequency synthesizer as recited in claim 54, wherein the integers N and M both vary on successive division cycles.

57. The frequency synthesizer as recited in claim 56, wherein the pairs of integers N and M are assigned values in a cyclic pattern designed to minimize any phase error of the output signal.

58. The frequency synthesizer as recited in claim 54, wherein variation of a gain of a control loop comprising the VCO, the phase comparator, and the output divider due to variation in the value of the output or reference integer N or M is reduced by weighting the phase error signal from the phase detector in proportion to the output or reference integer N or M.

59. The frequency synthesizer as recited in claim 54, wherein values of the output integer N and the reference integer M are constrained.

60. The frequency synthesizer as recited in claim 59, wherein the values of the output integer N and the reference integer M are each constrained between maximum and minimum values.

61. The frequency synthesizer as recited in claim 59, wherein one or more unacceptable values are determined for the values of the output integer N and the reference integer M.

62. A frequency synthesizer for generating an output signal of a desired output frequency comprising:

a reference frequency source for generating a reference signal having a reference frequency;

a reference divider circuit for dividing the reference signal by a reference divisor M and for producing a reference pulse train based on the divided reference signal;

a fractional controller for varying values of the reference divisor M and an output divisor N between a first pair of values (N1, M1) and a second pair of values (N2, M2), wherein the first and second pair of values (N1, M1) and (N2, M2) are selected such that a first ratio of the first pair of values is a close fractional approximation less than a ratio of the desired output frequency and the reference frequency and that a second ratio of the second pair of values is a close fractional approximation greater than the ratio of the desired output frequency and the reference frequency; and

an output processing circuit for generating the output signal based on the reference pulse train and an output pulse train; and

an output divider for dividing the output signal by the output divisor N and for producing the output pulse train based on the divided output signal.