Apparatus and method for a fast locking phase locked loop

• US 6,236,278 B1
• Filed: 02/16/2000
• Issued: 05/22/2001
• Est. Priority Date: 02/16/2000
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Olgaard, Christian
• Primary Examiner(s): MIS, DAVID C
• Application Number:
  US09/505,028
• Time in Patent Office: 461 Days
• Field of Search: 331/1.A, 331/16, 331/17, 331/18, 331/25, 331/DIG.2, 327/156-159, 360/50, 375/376, 455/260
• US Class Current: 331/25
• CPC Class Codes: H03L 7/0898 the source or sink current values being variable H03L7/0896 takes precedence
• CPC Class Codes: H03L 7/1072 by changing characteristics of the charge pump, e.g. changing the gain
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H03L 7/1972 for reducing the locking time interval H03L7/1974, H03L7/199 take precedence
• CPC Class Codes: H03L 7/1978 using a cycle or pulse removing circuit
• CPC Class Codes: Y10S 331/02 Phase locked loop having lock indicating or detecting means

Abstract

A control circuit for causing a phase lock loop (PLL) frequency synthesizer to achieve a fast phase lock time while also providing improved loop performance during normal phase locked operation. The phase locking time of the PLL is minimized by initially configuring the PLL to operate in a fractional mode with high frequency signals presented to the inputs of the loop phase detector, thereby producing a fast phase lock time. Once the PLL has achieved phase lock, its operation mode is transitioned to either an integer mode or an open loop mode without loss of phase lock, thus causing lower frequency signals or no signals, respectively, to be presented to the inputs of the loop phase detector and thereby significantly reducing spurious signal tones.

Claims

1. An apparatus including a dual mode control circuit for a phase lock loop (PLL), comprising:

a reference signal frequency divider circuit configured to couple to a PLL and receive at least one reference divider control signal and in accordance therewith receive and frequency divide an input reference signal having an input reference signal frequency and in accordance therewith provide one or more divided reference signals having one or more divided reference signal frequencies and phases;

a feedback signal frequency divider circuit configured to couple to said PLL and receive at least one feedback divider control signal and in accordance therewith receive and frequency divide a PLL feedback signal having a PLL feedback signal frequency and in accordance therewith provide one or more divided feedback signals having one or more divided feedback signal frequencies and phases; and

a control circuit, coupled to said reference and feedback signal frequency divider circuits, configured to couple to said PLL, receive a PLL lock signal from said PLL and receive and process one of said one or more divided feedback signals and in accordance therewith provide said at least one reference divider control signal and said at least one feedback divider control signal;

wherein said control circuit, in accordance with said PLL lock signal, and said reference and feedback signal frequency divider circuits, in accordance with said at least one reference divider control signal and said at least one feedback divider control signal, transition between first and second circuit operation modes when

said PLL lock signal indicates that said PLL has transitioned between unlocked and phase locked states of operation, and

said processing of said one of said one or more divided feedback signals indicates that a phase difference between said one of said one or more divided feedback signal phases and a desired signal phase transitions between outside and inside of a predetermined phase difference range.

2. The apparatus of claim 1, wherein said first and second circuit operation modes comprise fractional and integer frequency synthesis modes.

3. The apparatus of claim 1, wherein said divided feedback signal frequency is equal to said divided reference signal frequency.

4. The apparatus of claim 1, wherein said at least one reference divider control signal comprises a plurality of reference divider control signals and said reference signal frequency divider circuit comprises:

at least one counter circuit configured to receive a portion of said plurality of reference divider control signals and in accordance therewith receive and frequency divide said input reference signal and in accordance therewith provide a plurality of divided reference signals; and

a signal selector circuit, coupled to said at least one counter circuit, configured to receive another portion of said plurality of reference divider control signals and in accordance therewith receive all and provide one of said plurality of divided reference signals as said one or more divided reference signals.

5. The apparatus of claim 1, wherein said reference signal frequency divider circuit comprises a programmable counter circuit.

6. The apparatus of claim 1, wherein said at least one feedback divider control signal comprises a plurality of feedback divider control signals and said feedback signal frequency divider circuit comprises:

at least one counter circuit configured to receive a portion of said plurality of feedback divider control signals and in accordance therewith receive and frequency divide said PLL feedback signal and in accordance therewith provide a plurality of divided feedback signals; and

a signal selector circuit, coupled to said at least one counter circuit, configured to receive another portion of said plurality of feedback divider control signals and in accordance therewith receive all and provide one of said plurality of divided feedback signals as said one or more divided feedback signals.

7. The apparatus of claim 1, wherein said feedback signal frequency divider circuit comprises a programmable counter circuit.

8. The apparatus of claim 1, wherein said control circuit comprises first and second data registers configured to store first and second pluralities of data representing a numerator and a denominator of a fraction used in said processing of said one of said one or more divided feedback signals.

9. The apparatus of claim 8, wherein said control circuit further comprises a data processing circuit, coupled to said first and second data registers, configured to receive said one of said one or more divided feedback signals and in accordance therewith receive and process said first and second pluralities of data and in accordance therewith provide said at least one reference divider control signal and said at least one feedback divider control signal.

10. The apparatus of claim 9, wherein said data processing circuit comprises:

an accumulator circuit configured to receive said one of said one or more divided feedback signals and in accordance therewith receive and accumulate one of said first and second pluralities of data and a plurality of modulus data and in accordance therewith provide a plurality of accumulated data;

a modulus circuit, coupled to said accumulator circuit, configured to receive and perform a modulus operation upon said plurality of accumulated data and in accordance therewith provide said plurality of modulus data; and

a state comparison circuit, coupled to said modulus circuit, configured to receive and compare said modulus data and a plurality of predetermined state data representing a desired PLL operational state and in accordance therewith provide said at least one feedback divider control signal.

11. The apparatus of claim 1, further comprising a signal comparison circuit, coupled to said reference and feedback signal frequency divider circuits, configured to receive and compare said divided reference and feedback signals and in accordance therewith provide at least one PLL control signal representing a difference between said divided reference and feedback signal frequencies.

12. The apparatus of claim 11, wherein said signal comparison circuit comprises a phase detector circuit configured to compare said divided reference and feedback signal phases and in accordance therewith provide said at least one PLL control signal representing a difference between said divided reference and feedback signal phases.

13. The apparatus of claim 11, further comprising a signal filter circuit, coupled to said signal comparison circuit, configured to receive and filter said at least one PLL control signal and in accordance therewith provide a filtered control signal.

14. The apparatus of claim 13, further comprising a frequency-controlled signal source, coupled to said signal filter circuit, configured to receive said filtered control signal and in accordance therewith provide said PLL feedback signal.

15. The apparatus of claim 14, wherein said frequency-controlled signal source comprises a voltage-controlled oscillator circuit.

16. The apparatus of claim 1, wherein:

said control circuit is further configured to provide a loop control signal having first and second loop control signal states corresponding to when said PLL lock signal indicates that said PLL is in said unlocked and phase locked states of operation; and

said apparatus further comprises a signal comparison circuit, coupled to said control circuit and said reference and feedback signal frequency divider circuits, configured to receive said loop control signal and receive and compare said divided reference and feedback signals and in accordance therewith provide at least one PLL control signal representing a difference between said divided reference and feedback signal frequencies when said loop control signal is in said first loop control signal state.

17. The apparatus of claim 16, wherein said signal comparison circuit includes an output terminal which is configured to convey said at least one PLL control signal when said loop control signal is in said first loop control signal state and to operate in a high impedance state when said loop control signal is in said second loop control signal state.

18. A method of controlling a phase lock loop (PLL) in accordance with dual PLL operation modes, comprising the steps of:

coupling to a PLL;

receiving from said PLL a PLL feedback signal having a PLL feedback signal frequency;

receiving at least one reference divider control signal and in accordance therewith receiving and frequency dividing an input reference signal having an input reference signal frequency and in accordance therewith generating one or more divided reference signals having one or more divided reference signal frequencies and phases;

receiving at least one feedback divider control signal and in accordance therewith frequency dividing said PLL feedback signal and in accordance therewith generating one or more divided feedback signals having one or more divided feedback signal frequencies and phases;

receiving a PLL lock signal from said PLL and receiving and processing one of said one or more divided feedback signals and in accordance therewith generating said at least one reference divider control signal and said at least one feedback divider control signal; and

transitioning between first and second operation modes in accordance with said PLL lock signal, said at least one reference divider control signal and said at least one feedback divider control signal when

said PLL lock signal indicates that said PLL has transitioned between unlocked and phase locked states of operation, and

said processing of said one of said one or more divided feedback signals indicates that a phase difference between said one of said one or more divided feedback signal phases and a desired signal phase transitions between outside and inside of a predetermined phase difference range.

19. The method of claim 18, wherein said step of transitioning between said first and second operation modes comprises transitioning between fractional and integer frequency synthesis modes.

20. The method of claim 18, wherein said divided feedback signal frequency is equal to said divided reference signal frequency.

21. The method of claim 18, wherein said step of receiving at least one reference divider control signal and in accordance therewith receiving and frequency dividing an input reference signal having an input reference signal frequency and in accordance therewith generating one or more divided reference signals having one or more divided reference signal frequencies and phases comprises:

receiving a plurality of reference divider control signals as said at least one reference divider control signal;

receiving a portion of said plurality of reference divider control signals and in accordance therewith receiving and frequency dividing said input reference signal and in accordance therewith generating a plurality of divided reference signals; and

receiving another portion of said plurality of reference divider control signals and in accordance therewith receiving all and selecting one of said plurality of divided reference signals as said one or more divided reference signals.

22. The method of claim 18, wherein said step of receiving at least one reference divider control signal and in accordance therewith receiving and frequency dividing an input reference signal having an input reference signal frequency and in accordance therewith generating one or more divided reference signals having one or more divided reference signal frequencies and phases comprises:

programming a signal divisor in accordance with said at least one reference divider control signal; and

frequency dividing said input reference signal and in accordance therewith generating said one or more divided reference signals in accordance with said programmed signal divisor.

23. The method of claim 18, wherein said step of receiving at least one feedback divider control signal and in accordance therewith frequency dividing said PLL feedback signal and in accordance therewith generating one or more divided feedback signals having one or more divided feedback signal frequencies and phases comprises:

receiving a plurality of feedback divider control signals as said at least one feedback divider control signal;

receiving a portion of said plurality of feedback divider control signals and in accordance therewith receiving and frequency dividing said PLL feedback signal and in accordance therewith generating a plurality of divided feedback signals; and

receiving another portion of said plurality of feedback divider control signals and in accordance therewith receiving all and selecting one of said plurality of divided feedback signals as said one or more divided feedback signals.

24. The method of claim 18, wherein said step of receiving at least one feedback divider control signal and in accordance therewith frequency dividing said PLL feedback signal and in accordance therewith generating one or more divided feedback signals having one or more divided feedback signal frequencies and phases comprises:

programming a signal divisor in accordance with said at least one feedback divider control signal; and

frequency dividing said PLL feedback signal and in accordance therewith generating said one or more divided feedback signals in accordance with said programmed signal divisor.

25. The method of claim 18, wherein said step of receiving a PLL lock signal from said PLL and receiving and processing one of said one or more divided feedback signals and in accordance therewith generating said at least one reference divider control signal and said at least one feedback divider control signal comprises:

storing data representing a numerator and a denominator of a fraction; and

processing said one of said one or more divided feedback signals in accordance with said fraction.

26. The method of claim 25, further comprising the step of receiving said one of said one or more divided feedback signals and in accordance therewith receiving and processing said first and second pluralities of data and in accordance therewith generating said at least one reference divider control signal and said at least one feedback divider control signal.

27. The method of claim 26, wherein said step of receiving said one of said one or more divided feedback signals and in accordance therewith receiving and processing said first and second pluralities of data and in accordance therewith generating said at least one reference divider control signal and said at least one feedback divider control signal comprises:

receiving said one of said one or more divided feedback signals and in accordance therewith receiving and accumulating one of said first and second pluralities of data and a plurality of modulus data and in accordance therewith generating a plurality of accumulated data;

receiving and performing a modulus operation upon said plurality of accumulated data and in accordance therewith generating said plurality of modulus data; and

receiving and comparing said modulus data and a plurality of predetermined state data representing a desired PLL operational state and in accordance therewith providing said at least one feedback divider control signal.

28. The method of claim 18, further comprising the step of comparing said divided reference and feedback signals and in accordance therewith generating at least one PLL control signal representing a difference between said divided reference and feedback signal frequencies.

29. The method of claim 28, wherein said step of comparing said divided reference and feedback signals and in accordance therewith generating at least one PLL control signal representing a difference between said divided reference and feedback signal frequencies comprises comparing said divided reference and feedback signal phases and in accordance therewith generating said at least one PLL control signal representing a difference between said divided reference and feedback signal phases.

30. The method of claim 28, further comprising the step of filtering said at least one PLL control signal and in accordance therewith generating a filtered control signal.

31. The method of claim 30, further comprising the step of generating a frequency-controlled signal as said PLL feedback signal in accordance with said filtered control signal.

32. The method of claim 18, further comprising the steps of:

generating a loop control signal having first and second loop control signal states corresponding to when said PLL lock signal indicates that said PLL is in said unlocked and phase locked states of operation; and

comparing said divided reference and feedback signals and in accordance therewith generating at least one PLL control signal representing a difference between said divided reference and feedback signal frequencies when said loop control signal is in said first loop control signal state.

33. The method of claim 32, wherein:

said step of comparing said divided reference and feedback signals and in accordance therewith generating at least one PLL control signal representing a difference between said divided reference and feedback signal frequencies when said loop control signal is in said first loop control signal state comprises conveying said at least one PLL control signal via a signal terminal when said loop control signal is in said first loop control signal state; and

said method further comprises operating said signal terminal in a high impedance state when said loop control signal is in said second loop control signal state.