Computer graphics pixel rendering system with multi-level scanning

• US 6,236,408 B1
• Filed: 07/23/1998
• Issued: 05/22/2001
• Est. Priority Date: 01/10/1995
• Status: Expired due to Term

• Current Assignee: NVIDIA Corporation
• Original Assignee: Evans & Sutherland Computer Corp. (Elevate Entertainment, Inc.)
• Inventors: Watkins, Gary S.
• Primary Examiner(s): Cuchlinski, Jr., William A.
• Assistant Examiner(s): NGUYEN, THU V
• Application Number:
  US09/121,389
• Time in Patent Office: 1,034 Days
• Field of Search: 345/430, 345/433, 345/434, 345/440, 345/441, 345/426, 345/501, 345/505
• US Class Current: 345/582
• CPC Class Codes: G06T 11/40 Filling a planar surface by adding surface attributes, e.g. colour or texture
• CPC Class Codes: G06T 15/80 Shading

Abstract

A geometric processor provides object primitives, as triangles, in graphic display image space to support a dynamic display. The image space is defined by pixels, in turn specified in arrays as spans. In a multi-level scanning operation, primitives are scanned at a first level to locate lapped spans that are lapped by primitives. At a second level, spans are scanned to process pixels that are lapped by primitives. An alternative embodiment discloses three-level scanning in association with parallel pixel processing. Concurrent texturing structure operates along with cache memories.

Claims

1. A computer graphics process for scan processing object primitives to generate display pixels, as in a frame buffer, the pixels being organized in screen space having an associative space relationship with a display image space, said process including the steps of:

defining object primitives in relation to a plurality of panels, each panel including a plurality of span areas, each span area including a plurality of contiguous pixel areas of said display image space;

scanning said panels to locate span areas;

scanning said span areas to locate lapped spans, with lapped pixels within a primitive;

scanning pixels within said lapped spans to locate lapped pixels for processing; and

processing said lapped pixels as scanned, in parallel, span-by-span to provide pixel data in said frame buffer.

2. A computer graphics process according to claim 1, further including the step of defining a size of said span areas according to a size defined for said blocks of data received and transmitted by said interface.

3. A computer graphics process according to claim 1, further including the step of storing said blocks of pixel data received and transmitted by said cache.

4. A computer graphics process according to claim 3, further including the step of defining a size of said span areas according to a size defined for said blocks of data received and transmitted by said cache.

5. A computer graphics process according to claim 1, further including the steps of:

retrieving a block of texture data from a texture memory, said texture memory including an interface adapted to receive and transmit rectangular blocks of data; and

processing said block of texture data to provide texture for a span of said pixels.

6. A computer graphics process according to claim 1, wherein said step of processing said lapped pixels within each span further includes the steps of:

retrieving blocks of prior pixel data from said frame buffer;

processing said blocks of prior pixel data from said frame buffer to provide said blocks of pixel data.